DS_1209F_004
73S1209F Data Sheet
Rev. 1.2
77
RLength Count - was set for length of ATR
CLK
IO
RLength Interrupt
CLK Stop
CLK Stop Level
IO Bit
IODir Bit
TX/RX Mode Bit
TX = '1'
Data from Card -end of ATR
Data from TX FIFO
RLength
Count MAX
1. Interrupt generated when Rlength counter is MAX.
2. Read and clear Interrupt.
3. Set CLK Stop and CLK Stop level high in Interrupt routine.
4. Set TX/RX Bit to TX mode.
5. Reload Rlength Counter.
6. Set IO Bit low and IODir = Output. Since Rlen=(MAX or 0) and TX/RX =1, IO pin is controlled by IO bit.
7. Clear CLK Stop and CLK Stop level.
Note: Data in TX fifo should not be Empty here.
START Bit
Synchronous Clock Start/Stop Mode style Start bit procedure. This procedure should be used to
generate the start bit insertion in Synchronous mode for Synchronous Clock Start/Stop Mode protocol.
RLen=0
Rlen=1
2
1
3
7
6
5
6
4
Figure 21: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode
RLength Count
(Rlength = 9)
CLK
IO
RLength Interrupt
CLK Stop
CLK Stop Level
IO Bit
IODir Bit
TX/RX Mode Bit
TX = '1'
I2CMode = 1: Data to/from Card
I2CMode = 0: Data from TX fifo
I2CMode = 1:ACK Bit (to/from card)
I2CMode = 0: Data from TX fifo
RLength Count MAX
1. Interrupt generated when Rlength counter is MAX.
2. Read and clear Interrupt.
3. Set CLK Stop and CLK Stop level high, set IO Bit low and IODir = Output.
4. Set IO Bit High and IODir = Output.
5. Set TX/RX Bit to RX mode.
6. Reload Rlength Counter.
7. Clear CLK Stop and CLK Stop level.
STOP Bit
Synchronous Clock Start/Stop Mode Stop bit procedure. This procedure should be used to
generate the Stop bit in Synchronous Mode.
1
2
4
3
5
7
6
Min ½ ETU
Figure 22: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode
