Teridian 73S1209F, Datasheet

Page: 108 / 123

73S1209F Data Sheet DS_1209F_004
108 Rev. 1.2
Symbol Parameter
Condition Min Typ. Max Unit
Interface Requirements – Data Signals: I/O, AUX1 and AUX2.
V
OH
Output level, high (I/O,
AUX1, AUX2)
I
OH
=0 0.9 * V
CC
V
CC
+0.1 V
I
OH
= -40
μ
A 0.75 V
CC
V
CC
+0.1 V
V
OL
Output level, low (I/O, AUX1,
AUX2)
I
OL
=1mA
0.15 *V
CC
V
V
IH
Input level, high (I/O, AUX1,
AUX2)
0.6 * V
CC
V
CC
+0.30 V
V
IL
Input level, low (I/O, AUX1,
AUX2)
-0.15
0.2 *
V
CC
V
V
INACT
Output voltage when outside
of session
I
OL
= 0 0.1 V
I
OL
= 1mA 0.3 V
I
LEAK
Input leakage V
IH
= V
CC
10
μ
A
I
IL
Input current, low (I/O, AUX1,
AUX2)
V
IL
= 0 0.65 mA
I
SHORTL
Short circuit output current
For output low, shorted
to V
CC
through 33
Ω
15 mA
I
SHORTH
Short circuit output current
For output high,
shorted to ground
through 33
Ω
15 mA
t
R
, t
F
Output rise time, fall times
For I/O, AUX1, AUX2,
C
L
= 80pF, 10% to
90%.
100 ns
t
IR
, t
IF
Input rise, fall times 1
μ
s
R
PU
Internal pull-up resistor
Output stable for
>200ns
8 11 14
k
Ω
FD
MAX
Maximum data rate 1 MHz
Reset and Clock for Card Interface, RST, CLK
V
OH
Output level, high
I
OH
=-200
μ
A
0.9 * V
CC
V
CC
V
V
OL
Output level, low I
OL
=200
μ
A 0
0.15 *
V
CC
V
V
INACT
Output voltage when outside
of session
I
OL
= 0 0.1 V
I
OL
= 1mA 0.3 V
I
RST_LIM
Output current limit, RST 30
I
CLK_LIM
Output current limit, CLK 70 mA
CLK
SR3V
CLK slew rate V
CC
= 3V 0.3 V/ns
CLK
SR5V
CLK slew rate V
CC
= 5V 0.5 V/ns
t
R
, t
F
Output rise time, fall time
C
L
= 35pF for CLK,
10% to 90%
8 ns
C
L
= 200pF for RST,
10% to 90%
100 ns
δ
Duty cycle for CLK
C
L
=35pF,
F
CLK
≤
20MHz
45 55 %