VEEK-MT2 User Manual
32
www.terasic.com
July 4, 2016
A video source is input through an analog composite port on VEEK-MT2 which generates a digital
output in ITU BT656 format. A number of common video functions are performed on this input stream
in the FPGA. These functions include clipping, chroma resampling, motion adaptive deinterlacing, color
space conversion, picture-in-picture mixing, and polyphase scaling.
The input and output video interfaces on the VEEK-MT2 are configured and initialized by software
running on a Nios® II processor. Nios II software demonstrates how to control the clocked video input,
clocked video output, and mixer functions at run-time is also provided. The video system is
implemented using the QSYS system level design tool. This abstracted design tool provides an easy
path to system integration of the video processing data path with a NTSC or PAL video input, VGA
output, Nios II processor for configuration and control. The Video and Image Processing Suite
MegaCore functions have common open Avalon-ST data interfaces and Avalon Memory-Mapped
(Avalon-MM) control interfaces to facilitate connection of a chain of video functions and video system
modeling. In addition, video data is transmitted between the Video and Image Processing Suite functions
using the Avalon-ST Video protocol, which facilitates building run-time controllable systems and error
recovery.
shows the Video and Image Processing block diagram.
Figure 4-8 VIP Example SOPC Block Diagram (Key Components)
Summary of Contents for VEEK-MT2
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