Terasic TR10a-HL User Manual Download Page 73

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Figure 5-16 Block diagram of the fan speed control demonstration



Alarm Status Register Bit Assignments

When the fan is abnormal, the LED will lit. Users can refer to

Table 5-4

and get a better

understanding about the malfunction of the fansink accordingly. The status of BIT 4 ~ 7

can be ignored because BIT 4 is for MAX6651 only and BIT 5 ~ 7 are always low.

Table 5-4 Alarm-Enable Resgister Bit Masks



Design Tools



64-bit Quartus II v16.0.2



Demonstration Source Code



Project Directory: Demonstration\Fan



Bit Stream: TR10A_HL_golden_top.sof



Demonstration Batch File

Demo Batch File Folder:

\Fan\demo_batch

BIT

NAME

POR(DEFAULT)S

TATE

FUNCTION

7(MSB) to 5

---

Always 0

GPIO2

(MAX6651 only)

GPIO2 Alarm. Set when GPIO2

is low (MAX6651 only)

3(LED[3])

GPIO1

GPIO1 Alarm. Set when GPIO1

is low

2(LED[2])

TACH

Tachometer Overflow Alarm

1(LED[1])

MIN

Minimum Output Level Alarm

0(LED[0])

MAX

Maximum Output Level Alarm

Summary of Contents for TR10a-HL

Page 1: ...1...

Page 2: ...2 FPGA Configure Operation 54 4 3 Flash Programming with Users Design 55 4 4 Restore Factory Settings 56 Chapter 5 Peripheral Reference Design 58 5 1 Configure Si5340A B in RTL 58 5 2 Nios II control...

Page 3: ...3...

Page 4: ...tures integrated transceivers that transfer at a maximum of 12 5 Gbps allowing the TR10a HL to be fully compliant with version 3 0 of the PCI Express standard as well as allowing an ultra low latency...

Page 5: ...D and flash memory General user input output 8 LEDs 4 push buttons 2 dip switches Clock System 50MHz Oscillator Programmable clock generators Si5340A and Si5340B Memory QDRII SRAM FLASH Communication...

Page 6: ...board To provide maximum flexibility for the users all key components are connected with the Arria 10 GX FPGA device Thus users can configure the FPGA to implement any system design Figure 1 1 Block...

Page 7: ...B Blaster II for use with the Quartus II Programmer MAXII CPLD 5M2210 System Controller and Fast Passive Parallel FPP x32 configuration Memory devices 48MB QDRII SRAM 256MB FLASH General user I O 8 us...

Page 8: ...ector 40 Gbps PCI Express x8 edge connector Support for PCIe x8 Gen1 2 3 Edge connector for PC motherboard with x8 or x16 PCI Express slot Power Source PCI Express 6 pin DC 12V power PCI Express edge...

Page 9: ...oard Overview Figure 2 1 is the top and bottom view of the TR10a HL development board It depicts the layout of the board and indicates the location of the connectors and key components Users can refer...

Page 10: ...board USB Blaster II the following procedures show how to download a configuration bit stream into the Arria 10 GX FPGA Make sure that power is provided to the FPGA board Connect your PC to the FPGA...

Page 11: ...th the Embedded Blaster CPLD D8 Error Illuminates when the MAX II CPLD EPM2210 System Controller fails to configure the FPGA Driven by the MAX II CPLD EPM2210 System Controller D9 PAGE Illuminates whe...

Page 12: ...3 Position of DIP switch SW1 for Configure Mode Select Flash Image for Configuration The position 4 of DIP switch SW1 is used to specify the image for configuration of the FPGA Setting Position 4 of S...

Page 13: ...Arria 10 GX device Each push button provides a high logic level or a low logic level when it is not pressed or pressed respectively Table 2 3 lists the board references signal names and their corresp...

Page 14: ...matic Signal Names and Functions Board Reference Schematic Signal Name Description I O Standard Arria 10 GX Pin Number SW0 SW0 High logic level when SW in the UPPER position 1 8 V PIN_ BD28 SW1 SW1 1...

Page 15: ...30 2 4 Temperature Sensor and Fan Control The FPGA board is equipped with a temperature sensor TMP441 which provides temperature sensing These functions are accomplished by connecting the temperature...

Page 16: ...gulator Monitor and the Arria 10 GX FPGA The pin assignments for the associated interface are listed in109H109H Table 2 6 Table 2 6 Temperature Sensor and Fan Speed Control Pin Assignments Schematic S...

Page 17: ...libration value conversion times and averaging combined with an internal multiplier enable direct readouts of current in amperes and power in watts Table 2 7 shows the pin assignment of power monitor...

Page 18: ...two programming clock generators are low jitter oscillators which are used to provide special and high quality clock signals for high speed transceivers and high bandwidth memory Through I2C serial in...

Page 19: ...40G QSFP B port QSFPC_REFCLK_p 644 53125 MHz LVDS PIN_Y5 40G QSFP C port QSFPD_REFCLK_p 644 53125 MHz LVDS PIN_T5 40G QSFP D port U20 QDRIIA_REFCLK_p 275 MHz LVDS PIN_L9 QDRII reference clock for A p...

Page 20: ...G37 I2C bus connected with Si5340B Si5340B_I2C_SDA 1 8 V PIN_H31 Si5340B_RST 1 8 V PIN_G38 Si5340B reset signal Si5340B_INTR 1 8 V PIN_G32 Si5340B interrupt signal Si5340B_OE_n 1 8 V PIN_AL31 Si5340B...

Page 21: ...SH_A2 Address bus 1 8 V PIN_T12 FLASH_A3 Address bus 1 8 V PIN_H6 FLASH_A4 Address bus 1 8 V PIN_B14 FLASH_A5 Address bus 1 8 V PIN_A16 FLASH_A6 Address bus 1 8 V PIN_F6 FLASH_A7 Address bus 1 8 V PIN...

Page 22: ...bus 1 8 V PIN_C25 FLASH_D5 Data bus 1 8 V PIN_C32 FLASH_D6 Data bus 1 8 V PIN_C33 FLASH_D7 Data bus 1 8 V PIN_C35 FLASH_D8 Data bus 1 8 V PIN_B24 FLASH_D9 Data bus 1 8 V PIN_H35 FLASH_D10 Data bus 1 8...

Page 23: ...1 Ready of flash 1 1 8 V PIN_N17 2 8 QDRII SRAM The development board supports six independent QDRII SRAM memory devices for very high speed and low latency memory access Each of QDRII has a x18 inte...

Page 24: ...1 8 V HSTL Class I PIN_K8 QDRIIA_A18 Address bus 18 1 8 V HSTL Class I PIN_J9 QDRIIA_A19 Address bus 19 1 8 V HSTL Class I PIN_L6 QDRIIA_A20 Address bus 20 1 8 V HSTL Class I PIN_K6 QDRIIA_A21 Address...

Page 25: ...IA_Q12 Read Data bus 12 1 8 V HSTL Class I PIN_L14 QDRIIA_Q13 Read Data bus 13 1 8 V HSTL Class I PIN_L12 QDRIIA_Q14 Read Data bus 14 1 8 V HSTL Class I PIN_M13 QDRIIA_Q15 Read Data bus 15 1 8 V HSTL...

Page 26: ...A14 Address bus 14 1 8 V HSTL Class I PIN_E17 QDRIIB_A15 Address bus 15 1 8 V HSTL Class I PIN_G17 QDRIIB_A16 Address bus 16 1 8 V HSTL Class I PIN_G18 QDRIIB_A17 Address bus 17 1 8 V HSTL Class I PIN...

Page 27: ...a bus 8 1 8 V HSTL Class I PIN_E23 QDRIIB_Q9 Read Data bus 9 1 8 V HSTL Class I PIN_B23 QDRIIB_Q10 Read Data bus 10 1 8 V HSTL Class I PIN_A22 QDRIIB_Q11 Read Data bus 11 1 8 V HSTL Class I PIN_B22 QD...

Page 28: ...ess bus 9 1 8 V HSTL Class I PIN_C28 QDRIIC_A10 Address bus 10 1 8 V HSTL Class I PIN_B29 QDRIIC_A11 Address bus 11 1 8 V HSTL Class I PIN_B30 QDRIIC_A12 Address bus 12 1 8 V HSTL Class I PIN_C30 QDRI...

Page 29: ...V HSTL Class I PIN_T34 QDRIIC_Q3 Read Data bus 3 1 8 V HSTL Class I PIN_T35 QDRIIC_Q4 Read Data bus 4 1 8 V HSTL Class I PIN_P35 QDRIIC_Q5 Read Data bus 5 1 8 V HSTL Class I PIN_P36 QDRIIC_Q6 Read Dat...

Page 30: ...s bus 3 1 8 V HSTL Class I PIN_P33 QDRIID_A4 Address bus 4 1 8 V HSTL Class I PIN_L32 QDRIID_A5 Address bus 5 1 8 V HSTL Class I PIN_K32 QDRIID_A6 Address bus 6 1 8 V HSTL Class I PIN_R34 QDRIID_A7 Ad...

Page 31: ...IID_D15 Write data bus 15 1 8 V HSTL Class I PIN_F30 QDRIID_D16 Write data bus 16 1 8 V HSTL Class I PIN_G30 QDRIID_D17 Write data bus 17 1 8 V HSTL Class I PIN_G29 QDRIID_Q0 Read Data bus 0 1 8 V HST...

Page 32: ...s Schematic Signal Name Description I O Standard Arria 10 GX Pin Number QDRIIE_A0 Address bus 0 1 8 V HSTL Class I PIN_BB9 QDRIIE_A1 Address bus 1 1 8 V HSTL Class I PIN_BB8 QDRIIE_A2 Address bus 2 1...

Page 33: ...ite data bus 11 1 8 V HSTL Class I PIN_AR19 QDRIIE_D12 Write data bus 12 1 8 V HSTL Class I PIN_BD13 QDRIIE_D13 Write data bus 13 1 8 V HSTL Class I PIN_BD14 QDRIIE_D14 Write data bus 14 1 8 V HSTL Cl...

Page 34: ...HSTL Class I PIN_BD11 QDRIIE_ODT On Die Termination Input 1 8 V HSTL Class I PIN_BB13 QDRIIE_QVLD ValidOutput Indicator 1 8 V HSTL Class I PIN_AR17 Table 2 16 QDRII SRAM F Pin Assignments Schematic S...

Page 35: ...data bus 7 1 8 V HSTL Class I PIN_AD11 QDRIIF_D8 Write data bus 8 1 8 V HSTL Class I PIN_AC10 QDRIIF_D9 Write data bus 9 1 8 V HSTL Class I PIN_AA9 QDRIIF_D10 Write data bus 10 1 8 V HSTL Class I PIN...

Page 36: ...L Class I PIN_AE9 QDRIIF_K_n Clock N Differential 1 8 V HSTL Class I PIN_AD9 QDRIIF_CQ_p Echo clock P 1 8 V HSTL Class I PIN_AM8 QDRIIF_CQ_n Echo clock N 1 8 V HSTL Class I PIN_AM7 QDRIIF_RPS_n Report...

Page 37: ...a of channel 0 1 4 V PCML PIN_BB6 QSFPA_TX_P1 Transmitter data of channel 1 1 4 V PCML PIN_BC3 QSFPA_TX_N1 Transmitter data of channel 1 1 4 V PCML PIN_BC4 QSFPA_RX_P1 Receiver data of channel 1 1 4 V...

Page 38: ...B_TX_N1 Transmitter data of channel 1 1 4 V PCML PIN_AM2 QSFPB_RX_P1 Receiver data of channel 1 1 4 V PCML PIN_AL3 QSFPB_RX_N1 Receiver data of channel 1 1 4 V PCML PIN_AL4 QSFPB_TX_P2 Transmitter dat...

Page 39: ...N_U3 QSFPC_RX_N2 Receiver data of channel 2 1 4 V PCML PIN_U4 QSFPC_TX_P3 Transmitter data of channel 3 1 4 V PCML PIN_T1 QSFPC_TX_N3 Transmitter data of channel 3 1 4 V PCML PIN_T2 QSFPC_RX_P3 Receiv...

Page 40: ...QSFPD_LP_MODE Low Power Mode 1 8V PIN_AA12 QSFPD_INTERRUPT_n Interrupt 1 8V PIN_W13 QSFPD_MOD_PRS_n Module Present 1 8V PIN_Y12 2 10 PCI Express The FPGA development board is designed to fit entirely...

Page 41: ...Schematic Signal Names and Functions Schematic Signal Name Description I O Standard Arria 10 GX Pin Number PCIE_TX_p0 Add in card transmit bus 1 4 V PCML PIN_AV44 PCIE_TX_n0 Add in card transmit bus...

Page 42: ...card receive bus 1 4 V PCML PIN_AJ41 PCIE_RX_p5 Add in card receive bus 1 4 V PCML PIN_AG42 PCIE_RX_n5 Add in card receive bus 1 4 V PCML PIN_AG41 PCIE_RX_p6 Add in card receive bus 1 4 V PCML PIN_AE4...

Page 43: ...ions Schematic Signal Name Description I O Standard Arria 10 GX Pin Number RS422_DE Driver Enable A high on DE enables the driver A low input will force the driver outputs into a high impedance state...

Page 44: ...GX FPGA Table 2 23 Pin Assignments of 2x4 GPIO Header Schematic Signal Name Description I O Standard Arria 10 GX Pin Number GPIO0 GPIO Connection 0 1 8 V PIN_AT36 GPIO1 GPIO Connection 1 PIN_AT35 GPI...

Page 45: ...s II Project File qpf Quartus II Setting File qsf Top Level Design File v External PLL Controller v Synopsis Design Constraints file sdc Pin Assignment Document htm The System Builder not only can gen...

Page 46: ...s When users complete the settings the System Builder will generate two major files which include top level design file v and the Quartus II setting file qsf The top level design file contains top lev...

Page 47: ...ls SystemBuilder in the System CD Users can copy the entire folder to the host computer without installing the utility Please execute the SystemBuilder exe on the host computer as shown in Figure 3 2...

Page 48: ...eds If a component is enabled the System Builder will automatically generate the associated pin assignments including its pin name pin location pin direction and I O standards Note The pin assignments...

Page 49: ...n the Programmable Oscillator group as shown in Figure 3 5 QDRII or QSFP must be checked before users can start to specify the desired frequency in the programmable oscillators As the Quartus project...

Page 50: ...System Builder also provides functions to restore default setting load a setting and save board configuration file as shown in HFigure 3 6 Users can save the current board configuration information i...

Page 51: ...Si5340B External Oscillator Controller IP 3 Project name qpf Quartus II Project File 4 Project name qsf Quartus II Setting File 5 Project name sdc Synopsis Design Constraints File for Quartus II 6 Pro...

Page 52: ...B its controller will be instantiated in the Quartus II top level file as listed below If the dynamic configuration for the oscillator is required users need to modify the code according to users desi...

Page 53: ...h memory interface For the factory default code to run correctly and update designs in the user memory this memory map must not be altered Table 4 1Flash Memory Map Byte Address Block Description Size...

Page 54: ...flash 2 Set the FPGA configuration mode to FPPx32 mode by setting SW1 MSEL 0 2 as 000 as shown in Figure 4 1 3 Specify the configuration of the FPGA using the default Factory Configuration or User Con...

Page 55: ...to download TR10A_HL_PFL sof and launch batch flash_program sh flash_program sh Translate sof and elf into flash and programming flash with the generated flash file TR10A_HL sof Hardware design file...

Page 56: ...shown in Figure 4 5 2 In NIOS II processor options select FLASH as reset vector memory and specify 0x05E40000 as reset vector as shown in Figure 4 6 Figure 4 5 Flash Controller Settings in QSYS Figur...

Page 57: ...the FPGA to Factory Hardware by setting the FACTORY_LOAD dip in SW1 to the 1 position 9 Power on the FPGA Board and the Configure Done LED should light Except for programming the Flash with the defau...

Page 58: ...ystem CD 5 1 Configure Si5340A B in RTL There are two Silicon Labs Si5340 clock generators on TR10a HL FPGA board can provide adjustable frequency reference clock See Figure 5 1 for QSFP and QDRII int...

Page 59: ...e boxes of QSFP and QDRII interfaces Si5340 corresponding output channels will become available and users can select desired frequencies For example when checking QSFP A box See Figure 5 2 SI5340A QSF...

Page 60: ...top level file Configure SI5340A define SI5340A_POWER_DOWN 3 h0 define SI5340A_644M53125 3 h1 define SI5340A_322M265625 3 h2 define SI5340A_312M5 3 h3 define SI5340A_250M 3 h4 define SI5340A_156M25 3...

Page 61: ...fig_done assign SI5340A_OE_n 1 b0 assign SI5340A_RST_n CPU_RESET_n Configure SI5340B define REFCLK_QDR275 4 h0 define REFCLK_QDR250 4 h1 define REFCLK_QDR225 4 h2 wire si5340b_controller_start wire si...

Page 62: ...as shown in Figure 5 4 Figure 5 4 SDC file created by System Builder Using Si5340 control IP Table 5 1 lists the instruction ports of Si5340 Controller IP Table 5 1 Si5340 Controller Instruction Ports...

Page 63: ...project For example in Si5340A control IP change iPLL_OUT1_FREQ_SEL SI5340A_125M to iPLL_OUT1_FREQ_SEL SI5340A_156M25 Recompile project the Si5340A OUT2 channel for QSFP C output frequency will chang...

Page 64: ...users can refer to below steps to modify control IP register parameter settings to modify the IP to output a desired frequency 1 Firstly download ClockBuider Pro Software See Figure 5 5 which is prov...

Page 65: ...output frequency as shown in Figure 5 6 Figure 5 6 Define Output Clock Frequencies on ClockBuilder Pro Wizard 3 After the setting is completed ClockBuider Pro Wizard generates a Design Report text whi...

Page 66: ...lue See Figure 5 9 Figure 5 8 Sub Module file si5340a_i2c_reg_controller v Figure 5 9 Modify Si5340 Control IP Base on Design Report After modifying and compiling Si5340 can output new frequencies acc...

Page 67: ...h the on board temperature sensor System Block Diagram Figure 5 10 shows the system block diagram of this demonstration The system requires a 50 MHz clock provided from the board The four peripherals...

Page 68: ...e choice number Figure 5 11 Menu of Demo Program In temperature test the program will display local temperature and remote temperature The remote temperature is the FPGA temperature and the local temp...

Page 69: ...of QSFPA B C D REFCLK or control the Si5340B to configure the output frequency of QDRIIA B C D E F REFCLK according to your choice Demonstration File Locations Hardware project directory NIOS_BASIC_DE...

Page 70: ...sired output frequency of QSFPA B C D REFCLK as shown in Figure 5 14 For programmable PLL Si5340B test please input key 3 and press Enter in the nios terminal first then select the desired output freq...

Page 71: ...71 Figure 5 14 Si5340A Demo Figure 5 15 Si5340B Demo...

Page 72: ...ommunication The functions I2C_Config and I2C_Bus_Controller set and monitor the RPM of the fansink respectively A pre scaler is used as frequency divider for the clock frequency of I2C Users need to...

Page 73: ...s low Table 5 4 Alarm Enable Resgister Bit Masks Design Tools 64 bit Quartus II v16 0 2 Demonstration Source Code Project Directory Demonstration Fan Bit Stream TR10A_HL_golden_top sof Demonstration B...

Page 74: ...s installed on the host PC Connect the TR10a HL and the host PC via USB cable Install the USB Blaster II driver if necessary Power on the FPGA Board Execute the demo batch file test_ub2 bat under the...

Page 75: ...nded for compiling these projects 6 1 QDRII SRAM Test QDR II QDR II SRAM devices enable you to maximize memory bandwidth with separate read and write ports The memory architecture features separate re...

Page 76: ...unction block diagram of the demonstration The six QDRII SRAM controllers are configured as a 72Mb controller The QDRII SRAM IP generates a 550MHz clock as memory clock and a half rate system clock 27...

Page 77: ...PLL DLL and OCT resources The Arria 10 EMIF QDRII IP uses a Hard PHY and a soft Controller The Hard PHY capable of performing key memory interface functionality such as read write leveling FIFO buffer...

Page 78: ...demo batch files include the followings Batch file for USB Blaster II test bat FPGA configuration file TR10A_HL_golden_top sof Demonstration Setup Make sure Quartus II is installed on your PC Connect...

Page 79: ...y initializing the memory devices managing SRAM banks and keeping the devices refreshed at appropriate intervals System Block Diagram Figure 6 2 shows the system block diagram of this demonstration Th...

Page 80: ...ll show progress in JTAG Terminal when writing reading data to from the SRAM When verification process is completed the result is displayed in the JTAG Terminal Design Tools Quartus II 16 0 2 Nios II...

Page 81: ...on your PC Make sure both QDRII SRAMs are installed on the FPGA board Power on the FPGA board Use USB Cable to connect PC and the FPGA board and install USB Blaster II driver if necessary Execute the...

Page 82: ...82 Figure 6 3 Progress and Result Information for the QDRII Demonstration...

Page 83: ...Avalon MM DMA IP is used in this demonstration For detail about this IP please refer to Altera document ug_a10_pcie_avmm_dma pdf 7 1 PCI Express System Infrastructure Figure 7 1 shows the infrastruct...

Page 84: ...r which includes PCI Express Driver PCI Express Library PCI Express Examples The kernel mode driver assumes the PCIe vender ID VID is 0x1172 and the device ID DID is 0xE003 If different VID and DID ar...

Page 85: ...are specified under the hardware design on the FPGA 7 3 PCI Express Software Stack Figure 7 2 shows the software stack for the PCI Express application software on 64 bit Windows The PCI Express drive...

Page 86: ...PC 2 Make sure Altera Programmer and USB Blaster II driver are installed 3 Execute test bat in CDROM Demonstrations PCIe_Fundamental demo_batch to configure the FPGA 4 Restart windows operation system...

Page 87: ...in Figure 7 4 Figure 7 4 Dialog of Browse my computer for driver software 7 In the Browse for driver software on your computer dialog click the Browse button to specify the folder where altera_pcie_di...

Page 88: ...tall button Figure 7 6 Click Install in the dialog of Windows Security 9 When the driver is installed successfully the successfully dialog will appears as shown in Figure 7 7 Click the Close button Fi...

Page 89: ...E_AVMM h TERASIC_PCIE_AVMM DLL 64 bit DLL Below lists the procedures to use the SDK files in users C C project 1 Create a 64 bit C C project 2 Include TERASIC_PCIE_AVMM h in the C C project 3 Copy TER...

Page 90: ...verder ID and device ID Return Value Return a handle to presents specified PCIe card A positive value is return if the PCIe card is opened successfully A value zero means failed to connect the target...

Page 91: ...successful otherwise FALSE is returned PCIE_Write32 Function Write a 32 bit data to the FPGA Board Maximal write size is 4GB 1 bytes Prototype bool PCIE_Write32 PCIE_HANDLE hPCIE PCIE_BAR PcieBar PCIE...

Page 92: ...fy the target memory mapped address in FPGA pBuffer A pointer to a memory buffer to retrieved the data from FPGA The size of buffer should be equal or larger the dwBufSize dwBufSize Specify the byte n...

Page 93: ...data by given a byte offset Prototype bool PCIE_ConfigRead32 PCIE_HANDLE hPCIE DWORD Offset DWORD pdwData Parameters hPCIE A PCIe handle return by PCIE_Open function Offset Specify the target byte of...

Page 94: ...ncludes PCIE_FUNDAMENTAL exe TERASIC_PCIE_AVMM dll Demonstration Setup 1 Install the FPGA board on your PC as shown in Figure 7 9 Figure 7 9 FPGA board installation on PC 2 Configure FPGA with PCIE_Fu...

Page 95: ...PCIE_FUNDMENTAL exe A menu will appear as shown in Figure 7 11 Figure 7 11 Screenshot of Program Menu 7 Type 0 followed by a ENTERY key to select Led Control item then input 15 hex 0x0f will make all...

Page 96: ...TERY key to select Button Status Read item The button status will be report as shown in Figure 7 13 Figure 7 13 Screenshot of Button Status Report 9 Type 2 followed by an ENTERY key to select DMA Test...

Page 97: ...ndamental Visual C Project Demonstrations PCIe_SW_KIT PCIE_FUNDAMENTAL FPGA Application Design Figure 7 15 shows the system block diagram in the FPGA system In the Qsys Altera PIO controller is used t...

Page 98: ...e project includes the following major files Name Description PCIE_FUNDAMENTAL cpp Main program PCIE c Implement dynamically load for TERAISC_PCIE_AVMM DLL PCIE h TERASIC_PCIE_AVMM h SDK library file...

Page 99: ...E_AVMM h If developer change the Vender ID and Device ID and PCI Express IP they also need to change the ID value define in TERASIC_PCIE_AVMM h If the return value of PCIE_Open is zero it means the dr...

Page 100: ...trations PCIe_QDR demo_batch The folder includes following files FPGA Configuration File PCIe_QDR sof Download Batch file test bat Windows Application Software folder windows_app includes PCIE_QDR exe...

Page 101: ...s in Figure 7 17 Gen3 link speed and x8 link width are expected Figure 7 17 Screenshot of Link Info 8 Type 3 followed by an ENTERY key to select DMA On Chip Memory Test item The DMA write and read tes...

Page 102: ...I A Memory DAM Test Result 10 Type 5 followed by an ENTERY key to select DMA QDRII B Memory Test item The DMA write and read test result will be report as shown in Figure 7 20 Figure 7 20 Screenshot o...

Page 103: ...The DMA write and read test result will be report as shown in Figure 7 22 Figure 7 22 Screenshot of QDRII D Memory DAM Test Result 13 Type 8 followed by an ENTERY key to select DMA QDRII E Memory Test...

Page 104: ...Visual C 2012 Demonstration Source Code Location Quartus Project Demonstrations PCIE_QDR Visual C Project Demonstrations PCIe_SW_KIT PCIE_QDR FPGA Application Design Figure 7 25 shows the system block...

Page 105: ...al C 2012 The project includes the following major files Name Description PCIE_QDR cpp Main program PCIE c Implement dynamically load for TERAISC_PCIE_AVMM DLL PCIE h TERASIC_PCIE_AVMM h SDK library f...

Page 106: ...h If developer change the Vender ID and Device ID and PCI Express IP they also need to change the ID value define in TERASIC_PCIE_AVMM h If the return value of PCIE_Open is zero it means the driver c...

Page 107: ...107...

Page 108: ...nsceiver test code is used to verify the transceiver channels for the QSPF ports through an external loopback method The transceiver channels are verified with the data rates 10 3125 Gbps with PRBS31...

Page 109: ...al QSFP Cable Figure 8 2QSFP Loopback Fixture Figure 8 3 shows the FPGA board with two QSFP cable installed Figure 8 4 shows the FPGA board with four QSFP loopback fixtures installed Figure 8 3 Two QS...

Page 110: ...NOT powered on 3 Plug in the QSPF loopback fixtures 4 Connect your FPGA board to your PC with a mini USB cable 5 Power on the FPGA board 6 Execute test bat in the Transceiver_Test folder under your l...

Page 111: ...111 Figure 8 5QSFP Transceiver Loopback Test in Progress Figure 8 6QSFP Transceiver Loopback Done...

Page 112: ...e you can get help if you encounter problems Terasic Technologies 9F No 176 Sec 2 Gongdao 5th Rd East Dist HsinChu City Taiwan 30070 Email support terasic com Web www terasic com TE10a HL Web tr10a hl...

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