78
read back data with the regenerated data (the same sequence as the write data). Test
control signals for four QDRII+ SRAMs will generate from CPU_RESET_n and four
LEDs will indicate the test results of four QDRII+ SRAMs.
Altera QDRII and QDRII+ SRAM Controller with UniPHY
To use Altera QDRII+ SRAM controller, users need to perform the following steps in
order:
1. Create correct pin assignments for QDRII+.
2. Setup correct parameters in QDRII+ SRAM controller dialog.
Design Tools
Quartus II 16.0.2
Demonstration Source Code
Project directory: QDRII_x6_Test_550MHz
Bit stream used: TR10A_HL_golden_top.sof
Demonstration Batch File
Demo Batch File Folder: QDRIIx4_Test\demo_batch
The demo batch files include the followings:
Batch file for USB-Blaster II: test.bat,
FPGA configuration file: TR10A_HL_golden_top.sof
Demonstration Setup
Make sure Quartus II is installed on your PC.
Connect the USB cable to the FPGA board and host PC. Install the USB-Blaster II
driver if necessary.
Power on the FPGA Board.
Execute the demo batch file “test_ub2.bat” under the batch file folder,
QDRII_x6_Test_550MHz\demo_batch.
Press CPU_RESET_n of the FPGA board to start the verification process. When
CPU_RESET_n is held down, all the LEDs will be turned off. All LEDs should turn
back on to indicate test passes upon the release of CPU_RESET_n.
If any LED is not lit up after releasing CPU_RESET_n, it indicates the
corresponding QDRII+ SRAM test has failed.
Table 6-1
lists the matchup for the
four LEDs.
Press CPU_RESET_n again to regenerate the test control signals for a repeat test.
Summary of Contents for TR10a-HL
Page 1: ...1...
Page 3: ...3...
Page 71: ...71 Figure 5 14 Si5340A Demo Figure 5 15 Si5340B Demo...
Page 82: ...82 Figure 6 3 Progress and Result Information for the QDRII Demonstration...
Page 107: ...107...
