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3.2
General Design Flow
This section provides the detail procedures on how the System Build
This section will introduce the general design flow to build a project for the FPGA board
via the System Builder. The general design flow is illustrated in the
Figure 3-1
.
Users should launch System Builder and create a new project according to their design
requirements. When users complete the settings, the System Builder will generate two
major files which include top-level design file (.v) and the Quartus II setting file (.qsf).
The top-level design file contains top-level Verilog wrapper for users to add their own
design/logic. The Quartus II setting file contains information such as FPGA device type,
top-level pin assignment, and I/O standard for each user-defined I/O pin.
Finally, Quartus II programmer must be used to download SOF file to the FPGA board
using JTAG interface.
Figure 3-1Thegeneral design flow of building a project
Summary of Contents for TR10a-HL
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