DE1-SoC-MTL
2
User Manual
22
www.terasic.com
December 18, 2014
buffer driver fills up the DDR3 with data to be displayed, and the VIP frame-reader component
reads the data from the DDR3 in a DMA manner. The video data is streamed into the VIP Clocked
Video Output component. Finally, the VIP Clocked Video Output component drives the VGA DAC
chip to display the video data.
An I2C master controller in Qsys is used to communicate with the touch-screen panel. The
component interfaces with the touch-screen panel through I2C protocol.
The HPS communicate with the FPGA through AXI bridge. The components in FPGA are mapped
into user memory of the linux system through memory-mapped interface. Then the user software
can access the IPs in FPGA portion. The Quartus project is located under the folder
“Demonstrations/SoC_FPGA/MTL2_HPS” in the DE1-SoC-MTL2 system CD.
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Users can develop touch-screen GUI program based on the QT library. For more information,
please refer to the document “
Software Development Guide for touch-screen display.pdf
”
included in the DE1-SoC-MTL2 system CD. The precompiled libraries can be found from the
folder “Demonstrations/SoC_FPGA/Libraries” in the DE1-SoC-MTL2 system CD.
Summary of Contents for DE1-SoC-MTL2
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