DE1-SoC-MTL
2
User Manual
14
www.terasic.com
December 18, 2014
Figure 3-1 Signals of 2x20 GPIO connector
Table 3-1
shows the recommended pin assignments for the 2x20 GPIO pins in Quartus II.
Table 3-1 Recommended Pin Assignments of 2x20 GPIO in Quartus II
Pin Numbers
Pin Name
Direction
IO Standard
1
-
-
-
2
MTL_DCLK
Output
3.3-V LVTTL
3
-
-
-
4
MTL_R[0]
Output
3.3-V LVTTL
5
MTL_R[1]
Output
3.3-V LVTTL
6
MTL_R[2]
Output
3.3-V LVTTL
7
MTL_R[3]
Output
3.3-V LVTTL
8
MTL_R[4]
Output
3.3-V LVTTL
9
MTL_R[5]
Output
3.3-V LVTTL
10
MTL_R[6]
Output
3.3-V LVTTL
11
-
-
-
12
-
-
-
13
MTL_R[7]
Output
3.3-V LVTTL
14
MTL_G[0]
Output
3.3-V LVTTL
15
MTL_G[1]
Output
3.3-V LVTTL
16
MTL_G[2]
Output
3.3-V LVTTL
17
MTL_G[3]
Output
3.3-V LVTTL
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