NL865H2 Hardware Design Guide
1VV0301616 Rev. 7
Page
14
of
67
2020-04-20
3. PINS ALLOCATION
Warning:
NL865H2 is adopting a modified 56-pin xL865 Form Factor, pin to pin
compatible with the previous 48-pin xL865 FF and with 8 additional
pads.
The numbering of the pins has been changed accordingly and
attention has to be paid when comparing with previous 48-pin xL865
FF design.
Pin-out
Pin
Signal
I/O
Function
Type
Comment
Asynchronous Serial Port (USIF0)
– Prog. / Data + HW Flow Control
1
C109/DCD
O
Output for Data carrier detect signal (DCD) to
DTE
CMOS 1.8V
2
C125/RING
O
Output for Ring indicator signal (RI) to DTE
CMOS 1.8V
3
C107/DSR
O
Output for Data set ready signal (DSR) to DTE
CMOS 1.8V
4
C108/DTR
I
Input for Data terminal ready signal (DTR) from
DTE
CMOS 1.8V
5
C105/RTS
I
Input for Request to send signal (RTS) from DTE
CMOS 1.8V
6
C106/CTS
O
Output for Clear to send signal (CTS) to DTE
CMOS 1.8V
9
C103/TXD
I
Serial data input (TXD) from DTE
CMOS 1.8V
10
C104/RXD
O
Serial data output (RXD) to DTE
CMOS 1.8V
Auxiliary UART
52
RXD_AUX
I
Auxiliary UART (RX Data)
CMOS 1.8V
53
TXD_AUX
O
Auxiliary UART (TX Data)
CMOS 1.8V
