S50 Hardware User Guide
1VV0301505 Rev. 3
Page 17 of 60
2021-05-05
Not Subject to NDA
Warning: A pulldown resistor is programmed to CTS# if UICP is
disabled.
If AT+SYSTEMOFF is issued while UICP is disabled, it is necessary
that the host keeps CTS# at logic low or leaves this pin floating.
Otherwise the supply current drawn in the deep sleep mode
increases by VSUP/13k
Ω
, which would be at 3V 231µA, 770 times the
expected 0,3µA. This would reduce the lifetime of a coin cell
significantly.
4.3.2.
4-Wire Serial Interface
If the host in question is sufficiently fast, a four-wire scheme may be successful. Connect
the serial lines UART-RXD, UART-TXD as well as UART-RTS# and GND; leave UART-
CTS# open. The host is required to stop sending data within a short time after de-
assertion of UART-RTS# (there is room for up to 4 more characters at the time RTS#
drops).
UART-TXD
GND
UART-RXD
IUC_IN# / CTS#
UART-RXD
UART-TXD
CTS#
IUC_OUT# / RTS#
IUR_OUT#
IUR_IN#
Figure 6: UART Interface without UICP Signals 4-wire (incl. GND)
Warning: UICP must be deactivated permanently in this
configuration, because signal UART-CTS# and IUR-IN# become
inputs with no PU or PD if UICP is active. This would cause floating
CMOS inputs.
Note/Tip: It is strongly recommended to use hardware flow control in
both directions. Not using flow control can cause a loss of data.
