Tektronix TSG 95, Service Manual

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Theory of Operation
TSG 95 Service Manual
3–3
applies 0.2315 times VIN to the ADC input. The ADC reference voltage is 2.5 V
from (U20, A1
<
3
>
).
Another ADC input is used to monitor the ON key. Power is turned on by the
hardware without
m
P interaction; however, power is always turned off by the
m
P.
When the ON key is pressed, VIN is applied to the gate of Q2, which is normally
pulled down by R30. This causes Q2 to pull the input of the ADC down which is
normally pulled to +5 V through R2.
The MODE0, MODE1, STOP, and NMI pins are pulled up by R2.
The LCD is controlled by the microprocessor (U2) through connector J1, which
serves as a 4-bit data bus (UPD3..0) and control lines LCDE, LCDR/W, and
LCDRS. LCDE enables the LCD interface; LCDR/W selects whether a read or
write operation is being performed; and LCDRS selects whether an instruction or
data is being sent to the LCD.
R1 and R25 set the display contrast.
The LCD backlight power is applied through J6 by Q1 and R26. The on resis-
tance of Q1 and R26 sets the amount of current, and therefore brightness, of the
backlight.
Character generation is performed by the ASIC (U26). The character information
is loaded into U26 by the microprocessor (
m
P, U2).
The 27 MHz, temperature-compensated oscillator (TCXO) Y1 is the source of all
clocks in the system. U21 is used to buffer the output of the oscillator. The buff-
ered clock drives only the ASIC (U26). The ASIC generates a divide-by-two
clock (UPCLK) and its complement (UPCLK) to act as the clock for the
m
P. The
ASIC also generates a divide-by-eight clock (AUDCLK) for the tone chip (U12).
The DAC (U14, A1
<
3
>
) is driven by a delayed version of the 27 MHz clock.
The heart of the digital timing and signal generation is an ASIC (U26); see sche-
matic A1
<
2
>
. This chip generates addresses for the signal memory (U5 & U7),
processes data from that memory, generates characters, latches and decodes
m
P
addresses, acts as a
m
P interface, and generates a clock for the tone chip (U12,
A1
<
3
>
).
The test signals are broken down into eight point data segments. These segments
are stored in the RAM (U5). The eight segments are put together to form the test
signal. The ASIC gets the information to form video lines and frames from U7.
The lower four address lines of U5 are constantly addressed by the lower four
bits of the YC/horizontal counter. Counting off Cb, Y, Cr, Y to form eight points
of Y data in segments of multiplexed Y and C data. The lsb does the toggling
between Y and C data, while the next three bits count off the eight points.
LCD Display
Character Generation
Clock Generation
Digital Timing and
Signal Generation