Tektronix TLA7AA Series, Service Manual

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Theory of Operation
TLA7AXX/TLA7NAX Logic Analyzer Module Service Manual
3- 3
Clocking and triggering is controlled by a single ASIC. This ASIC determines
when acquisition data should be sampled based on the clock information and
qualifier information. The ASIC also contains 16 Event resources for the
purposes of word recognition, range recognition, and other trigger functions. In
merged configuration, the ASIC communicates information between modules to
ensure proper triggering.
The acquisition memory stores acquired data. The memory can be set up to store
all data samples, or it can be split to store data samples and either glitch
information or setup and hold violation information.
When the memory is split, only half the memory depth is available and can only
run at half the speed. Every stored data sample takes up two memory locations,
one to hold the actual data sample and the other to hold the corresponding glitch
information or the setup and hold information.
Glitch storage is only enabled with asynchronous clocking while setup and hold
storage is only enabled with synchronous clocking.
The trigger machine can trigger on either glitches or setup and hold violations
without storing information. This allows the user to trigger on a glitch or on a
setup and hold violation at maximum speed and maximum memory depth.
The backplane interface provides the interface with the mainframe and the
acquisition board. This interface contains intermodule signals that communicate
to other modules in the logic analyzer mainframe. The interface also provides the
10 MHz reference clock for the clocking circuitry.
Trigger and Storage
Control Circuitry
Acquisition Memory
Backplane Interface