Tektronix TLA 704, Service Manual

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Specifications
TLA 704 Color Portable Mainframe Service Manual
1–5
Table 1–3: Backplane interface (Cont.)
Characteristic Description
Inter-Module Latencies
6
All measurements typical.
LA to DSO Inter-Module System Trigger
3,7
358 ns + Smpl
LA to LA Inter-Module System Trigger
3,7
68 ns + Smpl
LA to DSO Inter-Module ARM
3
360 ns + Smpl
LA to LA Inter-Module ARM
3,8
108 ns + Smpl + Clk
LA to LA Inter-Module via Signal 1, 2
3,8,9
120 ns + Smpl + Clk
LA to LA Inter-Module via Signal 3, 4
3,8
116 ns + Smpl + Clk
DSO to DSO Inter-Module System Trigger
7
50 ns
DSO to LA Inter-Module System Trigger
7
–236 ns
DSO to LA Inter-Module ARM
8
–192 ns + Clk
DSO to DSO Inter-Module ARM 59 ns
DSO to LA Inter-Module via Signal 1, 2
8, 9
–179 ns + Clk
DSO to LA Inter-Module via Signal 3, 4
8
–184 ns + Clk
1
Includes typical jitter, slot-to-slot skew, and probe-to-probe variations to provide a “typical” number for the measurement.
Assumes standard accessory probes are utilized.
2
For time intervals longer than 1
m
s between modules, add 0.01% of the difference between the absolute time measure-
ments to the relative time correlation error to account for the inaccuracy of the CLK10 source.
3
“Smpl” represents the time from the event at the probe tip inputs to the next valid data sample of the logic analyzer. In
the normal internal clock mode, this represents the delta time to the next sample clock. In MagniVu internal clock mode,
this represents 500 ps or less. In external clock mode, this represents the time to the next master clock generated by the
setup of the clocking state machine and the supplied SUT clocks and qualification data.
4
DSO modules time correlation measured at maximum sample rate on channel one only.
5
All system trigger and external signal input latencies were measured from a falling-edge transition (active/true low) with
signals measured in the “wired-or” configuration.
6
Latencies are based on typical portable mainframe configurations consisting of two LA modules or an LA module plus a
DSO module. Latencies are system-configuration-dependent and may vary slightly with module loading.
7
In the Waveform window, triggers are always marked immediately except when delayed to the first sample. In the Listing
window, triggers are always marked on the next sample period following their occurrence.
8
“+Clk” represents the time to the next “master” clock at the destination logic analyzer. In the “asynchronous” or
“internal” clock mode, this represents the delta time to the next sample clock beyond the minimum async rate of 4 ns. In
the “synchronous” or “external” clock mode, this represents the time to the next master clock generated by the setup of
the clocking state machine and the supplied SUT clocks and qualification data.
9
Signals 1 and 2 (ECLTRG0, 1) are limited to a “broadcast” mode of operation, where only one source is allowed to drive
the signal node at any one time. That single source may be utilized to drive any combination of destinations.