Tektronix TDS7054, Service Manual

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Troubleshooting
6--70
TDS7104 & TDS7054 Service Manual
Table 6--13: Diagnostic LED
Diagnostic status
LED
Passed test Testing Test method
.8 MPC740 initialization,
MPC106 walking one test, or
MPC106 configuration test Walk a one through configuration register. Use addresses
FEC00000 and FEE00000. A one is walked through the lower
data bus.
Requests the vendor ID. Use addresses FEC00000 and
FEE00000. Vendor ID data is presented on the lower data bus.
Data 0x0face106 is written to the MPC740 register gpr2 if the
correct vendor ID is returned. If the incorrect ID is returned,
data 0x01bad106 is written to the register.
0 MPC740 initialization,
MPC106 walking one test, or
MPC106 configuration test First PCI access test and
UART initialize This is not a pass/fail test, only an attempt to read the PCI bus.
Read the configuration space of the SIO. The SIO should
return the vendor/device ID (0x00021057), within MPC740 gpr2
register. No data comparison or fault determination occurs. DIP
switches are not checked.
Set UART to 9600, n, 8, 1. No testing or fault reporting is
performed. Once completed, console is usable. Dip switches
are not checked.
1 First PCI access test and
UART initialize PC87560 walking-one Walk a one through the configuration register. Walk a one
through the AD bus.
2 PC87560 walking-one PC87560 configuration Request vendor/device ID. Data 0x0face560 is written to
MPC740 register gpr6 if correct ID is returned. If incorrect ID is
returned, data 0x01bad560 is written to MPC740 register gpr6.
3 PC87560 configuration DEC21554 configuration Request vendor/device ID. Data 0x0face215 is written to
MPC740 register gpr6 if correct ID is returned. If incorrect ID is
returned, data 0x01bad215 is written to MPC740 register gpr6.
4 DEC21554 configuration RS232 interface test Send UUUUUUUU (55hex, 1010101 binary) to console.
5 RS232 interface test ROM checksum Calculate device checksum and compare with checksum in
ROM.
6 ROM checksum DRAM cell test with cache Test address lines. Write patterns to address range set by
switch 1. From start address (000000000) to end address, write
hex pattern aaaaaaaa. Repeat for hex patterns cccccccc and
f0f0f0f0.
7 DRAM cell test with cache DRAM march test with out
cache DRAM march test. Test data lines. Write to address range set
by switch 1. Cache is disabled.
8 DRAM march test with out
cache DRAM march test with cache Test data lines. Write to address range set by switch 1.
9 DRAM march test with cache DRAM walking one Test data lines. Walk a one through DRAM memory location.
Cache is disabled. Walk a one through buss MEM_DL.
A DRAM walking one NVRAM walking one Walk a one through NVRAM memory location. Cache is
disabled. Walk a one through bus XPC_ISA_D.
H POST passed
L Boot parameters loaded and
waiting for host Program has loaded boot parameters and is waiting to connect
to host.