Tektronix RTX100A, Service Manual

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Specifications
RTX100A ISDB-T RF Signal Generator Service Manual
1-5
Table 1-2: Mainframe (Cont.)
Characteristics Description
PLL
Frequency 50 MHz to 100 MHz, locked to reference clock
Output clock 50 MHz maximum (serial clock)
26.75 MHz maximum (parallel clock)
Output rate 214 Mbps maximum
64 Kbps minimum
TS clock
(Internal and external
reference, 27 MHz and 10 MHz)
TS clock = (X / (2 * Y * Z) ) * 27 MHz
15362
<
X
<
31248
1686
<
Y
<
3376
2
≤
Z
≤
65536
(External parallel clock) TS clock = (X / (2 * Y * Z) ) * external parallel clock, 214 MHz maximum
15632
<
X
<
31248
1
<
Y
<
16383
2
≤
Z
≤
65536
(External serial clock) TS clock = (X / (2 * Y * Z) ) * external serial clock / 8,32 MHz maximum
15632
<
X
<
31248
1
<
Y
<
16383
2
≤
Z
≤
65536
P/N and Jitter (serial clock)
<
--104 dBc/Hz at 21.455707 MHz +20 kHz (RBW=300 Hz)
SPI interface
Connector type D-sub, 25 pin
Data rate 256 Kbps to 214 Mbps
Pin assignments 1 DCLK
2 GND
3 to 10 DATA 7 to DATA 0
11 DVALID
12 PSYNC
13 Shield
14 DCLK
15 GND
16 to 23 DATA 7 to DATA 0
24 DVALID
25 PSYNC
Output
Output level, typical 330 mV to 550 mV (termination: internal 100
Ω ,
external 100
Ω
), bus LVDS with 50
Ω
termination
Offset 1.1 V to 1.5 V
Output resistance, typical 100
Ω
, between differential outputs (output off)