Theory of operation
Integral clock recovery option on some models with internal coaxial
connection to the mainframe trigger, front panel clock and data output (not
all have data).
Communication with the mainframe for identi
fi
cation, control and
calibration/compensation storage.
The "system response" depends on the response of all of the components in the
signal path, from the front panel to the sampler. Bandwidth and reference receiver
responses are calibrated at the factory with a sub-picosecond optical impulse
applied to the front panel connector or with an optical heterodyne system. This
ensures that all instrument and module components are included, but also means
that instrument or module components cannot be replaced without performing
calibration.
Compensation performs a DC transfer curve characterization for each
bandwidth/reference receiver setting of a module. The curve data is stored in the
module EEPROM and is used to generate a look-up table in the mainframe. This
data corrects for linearity, gain and offset errors in the sampler.
Reference receivers can be created in any of the following ways:
A hardware
fi
lter inserted between the O/E and the sampler and dominates
the response.
No
fi
lter is used, but the bandwidth of the sampler is adjusted.
The O/E bandwidth is adjusted and dominates the response.
The power monitor is a second measure of the photo-diode current that is
independent of the sampler signal path. Analog circuitry continuously senses the
current
fl
owing into the bias side of the photo diode. The signal is ampli
fi
ed
by a programmable gain ampli
fi
er and input to an 8-bit AD converter. The AD
converter and ampli
fi
er are controlled through the I
2
C interface.
Power meter compensation performs two functions:
Two offset inputs are adjusted in the ampli
fi
er so that the signal stays in range
for all of the gain settings.
Offset is measured for all gain settings and stored so it can be subtracted
from the raw measured current. Because the measurements are made
through independent paths the power monitor is useful in debugging
module/mainframe problems.
Clock recovery
Many 80C00 modules have integral clock recovery (standard or as an option),
with internal coaxial connection of the recovered clock signal to the mainframe
trigger, front panel clock and data output connectors (not all have data).
8
DSA8300 Digital Serial Analyzer and Modules Service Manual
