Tektronix 2215, Instruction Manual

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algebraic sum o f the tw o vertical signals.
The Add Enable c ircu it, composed o f Q316, U197C,
and U 315A, is activated when both Diode Gates are turned
on fo r an Add vertical display. W ith the Q and Q outputs
o f U 317A H I, the o u tp u t o f U 315A w ill be LO and tra n ­
sistor Q316 is biased on. The co lle cto r o f Q316 rises tow ard
+5 V and U197C is biased on. Transistor U197C supplies
the additional current required to keep both Diode Gates
forw ard biased and to supply the proper dc level to the
Delay Line Driver input. Bypass capacitor C316 prevents
sw itching transients fro m being introduced in to the Delay
Line Driver by the Add Enable circu it.
When S315 is set to A L T , a HI is placed on both the Set
and Reset inputs o f U 317A. F lip -flo p U 317A w ill transfer
the logic level on the D in p u t (pin 2) to the Q o u tp u t
(pin 5) on each clock-pulse rising edge. Pin 1 o f NAND-gate
U 310A is held HI by the Chop O scillator o u tp u t, and pin 2
fo llo w s the A lt Sync signal produced by the H o ld o ff
c irc u itry in the A Sweep Generator (Diagram 5). The
o u tp u t o f U 310A (pin 3) is therefore an inverted A lt Sync
pulse. The signal on the D in p u t o f U 317A (pin 2) fo llo w s
the logic level set by the Q o u tp u t pin. As each clock pulse
occurs, the states o f the Q and Q o utputs reverse (toggle),
enabling Channel 1 and Channel 2 Diode Gates alternately
w ith each sweep.
CHOP OSCILLATOR.
Setting S315 to CHOP enables
the Chop Oscillator and the Chop Blanking c ircu it. Pins C
and D o f S315 are connected to place a
LO
logic level on
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