AINTERLOCK ACTIVATION AND MANAGEMENT
The TEA2261 has a strobed current interlock at Pin 3 and an interlock related
to the power supply voltage at Pin 16.
An image of the current is collected at the terminals of emitter resistor RP020,
and applied to Pin 3 of TEA2261. The following two thresholds apply:
1ST THRESHOLD INTERLOCK
When the voltage at Pin 3 reaches the first threshold, 0.6 V, TP060 is blocked
until the next Tb pulse (bit-by-bit limitation). During this time, CP063 is
charged by a current of 45 - 10 = 35 µA.
When this phenomenon is repetitive, the charge on CP063 reached 2V6 and
triggers an RS-bistable circuit which permanently disables control of TP060.
A main reset is then necessary to re-start the circuit (Vdc 5V5).
2ND THRESHOLD INTERLOCK
In the event of a major overload (short circuit on USYS), a second threshold
is reached (0V9). Control of TP060 is permanently disabled. A main reset is
then necessary to re-start the circuit (V Pin 16 5V5).
VOLTAGE INTERLOCK
A voltage above 15V7 on Pin 16 blocks TP060. A main reset is then
necessary to re-start the circuit (V Pin 16 5V5).
SPECIFIC FEATURES OF ICC19 CHASSIS
Because the primary interlock is calibrated for U SYS at steady state, the
sensitivity of this stage has been increased in Standby Mode to detect faults
on the other secondaries.
For this purpose, a resistor, RP065, is added between the error amplifier
output of the primary loop (Pin 7 of IP060) and the interlock input (Pin 3).
When capacitor CP063 reaches 0.6 V, Transistor TP027 conducts and
reduces the charging current of Capacitor CP060 (RP059), which reduces
the frequency of the Standby oscillator.
NOTES :
CENTRE DE
FORMATION TECHNIQUE
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Summary of Contents for ICC19
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