TDT RZ2, Manual

Page: 43 / 736

System 3 1-37
RZ6 Multi I/O Processor
As shown in the diagram above, the RZ6 architecture consists of three
functional blocks:
The DSPs
Each DSP in the DSP block is connected to three data
buses: two buses that connect each DSP to the other
functional blocks and one that handles data transfer between
the DSPs (the zHop Bus). This architecture facilitates fast
DSP-to-off-chip data handling.
Each standard DSP is connected to 64 MB SDRAM and
each core in a QZDSP is connected to 256 MB DDR2.
Large and complex circuits should be designed to balance
memory needs (such as data buffers and filter coefficients)
across processors.
When designing circuits also note that the maximum number
of components for each RZ6 standard RZDSP is 768 and
1000 for each QZDSP.
The zBus Interface The zBus interface provides a connection to the PC. Data
and host PC control commands are transferred to and from
the DSP Block through the zBus Interface Bus.
The I/O Interface The I/O interface serves as a connection to outside signal
sources or output devices. It is used to input data from the
optional preamplifier input and digital and analog channels.
The I/O interface bus provides a direct connection to each
DSP.
Distributing Data Across DSPs
To take advantage of multi-DSP modules, processing tasks must be efficiently
distributed across the available DSPs (or among cores of a quad-core DSP). The
RZ6 architecture provides the zHop bus for transferring data across DSPs.
The zHop Bus
The zHop bus allows the transfer of single or multi-channel signals between each
DSP in the RZ6.
In RPvdsEx, data is transferred across the zHop bus using paired zHop components,
including zHopIn, zHopOut, MCzHopIn, MCzHopOut, and MCzHopPick. Up to 126
pairs can be used in a single RPvdsEx circuit. Bus Related Delays
The zHop Bus introduces a two sample delay. This delay is taken care of for the
user in Synapse, BiosigRZ, and in OpenEx (when Timing and Data Saving macros
are used).