Tait TB9100, Service Manual, Page: 92 / 132

92 RF Circuitry TB9100 Reciter Service Manual
© Tait Electronics Limited January 2006
6.2.3 IF Circuitry
The signal from the mixer is fed to the IF amplifier through a 4-pole crystal
filter which provides protection from strong off-channel signals. The IF
amplifier is a two-transistor design with voltage and current feedback, which
provides sufficient gain to drive the digital receiver. The 70.1MHz signal is
finally passed to the analog-to-digital converter (ADC) in the digital receiver
via an anti-alias filter. This filter prevents IF noise at frequencies other than
70.1MHz, generated in the amplifier, from being sampled by the ADC at
other Nyquist zones.
6.2.4 Synthesizer
The receiver synthesizer consists of a programmable frequency synthesizer
IC, the receiver VCO, and a stable known reference.
The synthesizer uses a phase-locked loop to lock the receiver VCO to a
stable known frequency reference. The synthesizer IC receives the divider
and control information from the RISC processor via a 3-wire serial bus
(clock, data and enable). When the data bits are latched in, the synthesizer
processes the incoming signals from the VCO feedback signal (f
vcofb
) and
the reference oscillator (f
ref
).
The VCO feedback attenuator is a resistive divider that terminates the VCO
feedback signal in a fixed low impedance (50
Ω
). This attenuates the VCO
RF level down to a level suitable for the RF prescaler (within the synthesizer
IC).
A 12.8MHz temperature controlled crystal oscillator (TCXO) is used as the
internal reference oscillator. When the TCXO is active, the receiver
synthesizer is locked to an “internal reference mode” (by default).
Alternatively, a phase-locked 12.8MHz voltage controlled crystal oscillator
(VCXO) can be used as the external reference oscillator. When the VCXO
is active, the receiver synthesizer is locked to an “external reference mode”.
In operation only one oscillator is active at any given time. Refer to
“Reference Switch” on page 29 for details on the phase-locked 12.8MHz
external reference oscillator.
The reference oscillators are buffered, branched, and divided down to the
6.25kHz (default) or 5 kHz divider reference within the synthesizer IC.
The same divider reference is maintained by dividing the VCO feedback
signal using the prescaler and programmable dividers of the synthesizer IC.
Phase lock is achieved when both divider references have the same phase and
frequency content (i.e. their difference is zero or DC). This is achieved by
the phase detector (part of the synthesizer IC), which compares both divider
references and delivers an error signal. A
±
4 mA charge pump circuit (also
part of the synthesizer IC) and the active loop filter circuit convert this error
signal to a DC voltage (0 to 22 V
1
) to tune the VCO for correction.
1. The normal lock range is between 3V and 16V.