Tait TB9100 Service Manual Download Page 117

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TB9100 Reciter Service Manual

Appendices

117

L1ST3
L1RQb

PC13

E18

I/O

Output strobe from the serial interface
D-channel request signal for serial interface TDMb

General-purpose I/O port C, bit 13

L1ST4
L1RQA

PB16

PHREQ[0]
RXADDR0

N16

I/O

Output strobe from the serial interface
D-channel request signal for serial interface TDMa

General-purpose I/O port B, bit 16

Most significant bit of PHY request bus
UTOPIA multi-PHY receive address line 0

L1ST4
L1Rqa

PC12

F18

I/O

Output strobes from the serial interface
D-channel request signal for serial interface TDMa.

General-purpose I/O port C, bit 12

L1SYNCB
PC6

R19

I/O

Receive sync input for the serial interface TDMb
General-purpose I/O port C, bit 6

L1TCLKB
TOUT4
CLK8

PA0

U19

I/O

Transmit clock for the serial interface TDMb
Timer 4 output
Clock input for SCCs and SMCs.

General-purpose I/O port A, bit 0

L1TSYNCB
PC7
SDACK2

M16

I/O

Transmit sync input for serial interface TDMb
General-purpose I/O port C, bit 7
SDMA acknowledge 2 output

L1TxDA

PA9

K18

I/O

Transmit data O/P for the serial interface TDMa

General-purpose I/O Port A, bit 9

L1TxDB

PA11

G16

I/O

Transmit data O/P for serial interface TDMb

General-purpose I/O port A, bit 11

MII_MDIO

H18

I/O

MII management data

MII_COL

I/P

MII collision

MII_CRS

I/P

Input MII carrier receive sense

MIIMDC

L1RSYNCB
PD12
UTPB[3]

R16

I/O

Media independent interface management data clock

Input receive data sync signal to TDM channel B
General-purpose I/O port D, bit 12
UTOPIA bus bit 3 input/output signal

MIIRXCLK

MIIMDC
PD8

W17

I/O

Media independent interface receive clock

Media independent interface management data clock
General-purpose I/O port D, bit 8

MIIRXD0

PD10
TXENB

W18

I/O

Media independent interface receive data 0

General-purpose I/O port D, bit 10
Transmit enable output signal

MIIRXD1

L1TSYNCB
PD13
UTPB[2]

V18

I/O

Media independent interface receive data 1

Input transmit data sync signal to TDM channel B
General-purpose I/O port D, bit 13
UTOPIA bus bit 2 input/output signal

MIIRXD2

L1RSYNCA
PD14
UTPB[1]

V19

I/O

Media independent interface receive data 2

Input receive data sync signal to TDM channel A
General-purpose I/O port D, bit 14
UTOPIA bus bit 1 input/output signal

Table 8.10

MPC859T Port Assignments (Continued)

Pin Name

Pin No.

Type

Function

Summary of Contents for TB9100

Page 1: ...TB9100 base station Reciter Service Manual MBA 00017 01 Issue 1 January 2006...

Page 2: ...ct Technical Support E mail support taitworld com Website http support taitworld com To our European customers Tait Electronics Limited is an environmentally responsible company which supports waste m...

Page 3: ...k Board 13 1 1 Equipment Required 13 1 2 Troubleshooting 14 1 3 Before You Start 15 1 4 Removing the Faulty Board 16 1 5 Replacing the Board 16 1 6 Restoring the Configuration 18 2 Reciter Circuit Des...

Page 4: ...6 RF Circuitry 87 6 1 Receiver RF Circuitry VHF Reciter 87 6 2 Receiver RF Circuitry UHF Reciter 91 6 3 Exciter RF Circuitry 94 7 Power Supply 101 7 1 RF PCB 101 7 2 Digital PCB 101 8 Appendices 103 8...

Page 5: ...pment or this manual or both without prior notice Copyright All information contained in this manual is the property of Tait Electronics Limited All rights are reserved This manual may not in whole or...

Page 6: ...to limitations of the schematic editor active low signal names have been indicated on the schematics with an _N suffix Hexadecimal numbers are indicated with a 0x prefix Binary numbers are indicated w...

Page 7: ...n audio interface with separate cable pairs for transmit and receive signals APCO Association of Public Safety Communications Officers a US body of public safety communications users eg Police Fire wh...

Page 8: ...al Equipment DTLB Data Translation Lookaside Buffer DTR Data Terminal Ready E M Ear and Mouth a simple DC signalling scheme used in telecom networks E2PROM Electrically Erasable Programmable Read Only...

Page 9: ...a higher memory address than the most significant byte c f Big Endian LRU Least Recently Used a method of updating cache memory contents lsb Least significant bit LSU Load Store Unit LVTTL Low Voltage...

Page 10: ...CC Quad Integrated Communications Controller a version of a CPM Reciter Receiver Exciter the RF signal handling parts of the base station excluding the power amplifier RISC Reduced Instruction Set Com...

Page 11: ...plex Telco Telephone Company TSA Time Slot Assigner TTL Transistor Transistor Logic an early bipolar logic family Tx Transmit TxD Transmit Data UART Universal Asynchronous Receiver Transmitter UPM Uni...

Page 12: ...12 TB9100 Reciter Service Manual Tait Electronics Limited January 2006...

Page 13: ...board Servicing procedures for the reciter digital board and the reciter RF board are covered in the TB8100 Service Manual 1 1 Equipment Required Anti static work environment PC with Ethernet cable T...

Page 14: ...and check the flexible connector it supplies power to the network board Replace if faulty see step 5 on page 17 b If the PowerPC LED is flashing quickly 2 Hz the operating sys tem kernel is running I...

Page 15: ...re and or kernel to see if this fixes the problem a If possible use the CSS to upload the firmware b Otherwise follow TN 997 to replace the kernel and or the firmware using telnet and a TFTP server 6...

Page 16: ...or break solder joints If the board is a snug fit on the locating pins you may have to very gently lever the board with a screwdriver beginning at the right hand side as viewed in Figure 1 1 to get it...

Page 17: ...he flexible connector as shown in Figure 1 2 If required fit a new flexible cable It must be correctly formed to prevent excessive stress on the cable or the connector Make sure that the cable is prop...

Page 18: ...the reciter using the correct IP address network boards are given the IP address 192 168 1 2 in the factory 2 Restore the base station s configuration overwriting the IP address 3 Reset the reciter On...

Page 19: ...bands or sub bands and these are identified with the letters listed in the following table The reciter comprises three PCBs an RF a digital and a network PCB These PCBs are mounted on a central chass...

Page 20: ...r Subsystem Reference Frequency Subsystem Digital Receiver Power Supply Power Supply RISC DSP RISC CODECs IF 12 8MHz Ref RF I P 28VDC I P 28V 28V 5V 3 3V 8 5V RF O P PA Key Audio System Control Bus Sy...

Page 21: ...chieved by digital mixing with a numerically controlled oscillator NCO The mixing process is done using in phase and quadrature methods to achieve image rejection and allows channel filtering to be ap...

Page 22: ...xed point There are 96 kilobytes of on chip program memory and 64 kilobytes of on chip data memory Although no external memory is used the external memory interface is connected to the DDC for initial...

Page 23: ...cted to the three CODECs encoder decoder Serial port 3 is not used 3 2 4 CODECs The three CODECs provide the audio frequency analog interface to the reciter There are six analog input and six analog o...

Page 24: ...Audio DC Measurement Noise Mute serial port Interface RISC DSP RISC serial port CODECs Signal Conditioning serial port CODECs Signal Conditioning serial port Tx VCO Tx Synthesiser Tx VCXO RF Frequenc...

Page 25: ...l inputs and outputs are as follows chip select signals to synthesizers out of lock signals from synthesizers external reference detection internal external reference selection Rx Gate output Tx Relay...

Page 26: ...External Reference Detect Select RISC 40MHz Clock Synthesizers Flash RAM DSP System Control Bus ASIF PCB Interrupt Interrupt Main Loop Debug LEDs DIP Switch SPI SPI Chip Selects Chip Selects Lock Det...

Page 27: ...or signal conditioning CSS communication via the RS 232 interface fan good indication front panel fans Note that the volume control on the control panel is analog only and is not controlled by the RIS...

Page 28: ...h continuously monitors and maintains the 40MHz VCXO to a fixed frequency and constant phase relationship with respect to a 12 8MHz reference The 40MHz VCXO oscillator is electrically tuned using two...

Page 29: ...ference is detected buffered and divided down to the 100kHz divider reference within the synthesizer IC The same divider reference is maintained by dividing the 12 8MHz VCXO feedback buffered signal u...

Page 30: ...erence 12 8MHz TCXO and shuts down the external reference 12 8MHz VCXO When the switch is on it powers up the external reference 12 8MHz VCXO and shuts down the internal reference 12 8MHz TCXO 4 3 3 D...

Page 31: ...ef f VCOfb Software Register External Reference Detector Lock Detect RISC 8 9 Prescaler Frequency Synthesizer IC Loop Filter External Reference 12 8MHz VCO Clock Data Chip Select Latch Enable Serial B...

Page 32: ...32 Reference Switch TB9100 Reciter Service Manual Tait Electronics Limited January 2006...

Page 33: ...net interface and the audio and E M interface blocks to connect to the outside world These interfaces provide signal formatting signal level conversion I O protection etc for the logic level signals e...

Page 34: ...e DSP The power supply block contains several power convertors that convert the incoming 28V supply to the various power supply voltages required by the ASIF circuitry The power supply block also incl...

Page 35: ...rd as it is used for factory loading of the initial bootloader code JTAG connector J106 is only fitted to prototype boards used for debugging of DSP code It cannot be fitted to production boards as it...

Page 36: ...x 2 j CODECs 1 SRAM 1 RISC JTAG connector factory use only 1 flash memory 1 RISC 1 DSP 1 DSP JTAG connector factory use only 1 main digital system 1 power supply 1 digital IF and clock 1 DDC 2 ADC 2...

Page 37: ...TB9100 Reciter Service Manual Network Circuitry 37 Tait Electronics Limited January 2006 b j 1 1 1 1 1 1 1 1 2 2 2 2 2 2 1 i 2 c d e f g h 1 2 2 2 3 3 3...

Page 38: ...stead of the four fitted to the MPC866 The block diagram Figure 5 2 shows the internal structure refer to the MPC866 data sheet reference 1 and MPC866 user s manual reference 2 for full details of the...

Page 39: ...lly to the PowerPC and to external memory and peripherals The performance is further enhanced by pipelining instruction fetching and execution Instructions are pre fetched from memory and pre decoded...

Page 40: ...uction and data caches each with separate data and address buses This allows data and instruction fetches from the caches to occur simultaneously Although the internal structure of the instruction and...

Page 41: ...service software or can be configured to start debug mode Once debug mode is activated the processor core fetches its instructions from the debug interface rather than program memory This allows the...

Page 42: ...e 160MHz to 266MHz The CPU clock defaults to the PLL clock divided by 2 although higher division ratios are available where it is desired to run the CPU at a lower clock frequency to save power Other...

Page 43: ...time base are 16 32 and 64 bit counters respectively They can be used to generate interrupts at specific times and are mainly used for operating system timing functions Interrupts Four of the eight l...

Page 44: ...n MPC Reset The MPC supports several levels of resets that can be initiated internally to the MPC or driven by external devices The different levels of resets are primarily used to enable software deb...

Page 45: ...his feature is used only for the BDM debug port connected to J100 see Debug Facilities and Program Loading on page 41 Pull up resistors R201 and R203 ensure correct high logic levels when no device is...

Page 46: ...s nor mal industry convention ie the lsb is D0 rather than the Pow erPC convention with D31 being the lsb The transition from PowerPC numbering order to normal numbering order occurs at the MPC extern...

Page 47: ...ic follows the normal industry convention ie the lsb is A0 rather than the PowerPC convention with A31 being the lsb The transition from PowerPC numbering order to normal numbering order occurs at the...

Page 48: ...lers on page 49 to determine the cycle type Some are available on test points to facilitate hardware and program debugging When the memory or peripheral devices has output input the data to from the b...

Page 49: ...om the rising edge of the clock Similarly all control inputs must be set up at a suitable time prior to the rising edge of CLKOUT to be recognized during the next clock cycle Memory Controllers The MP...

Page 50: ...hip select The assignment is controlled via internal MPC registers which also allocate a particular address range to a device and sets other parameters such as address type bus width parity enable and...

Page 51: ...Host Port Interface HPI on page 69 In the event that the HRDY signal does not terminate the bus cycle within approximately 32us the bus cycle times out and is terminated by the bus monitor see Time Ba...

Page 52: ...e is terminated abnormally by a TEA see MPC Bus Cycles on page 48 or bus monitor time out see Time Bases and Watchdog on page 42 Its function is to allow the UPM to clean up after an incomplete memory...

Page 53: ...dress and other relevant settings Thereafter the FEC handles the necessary transmit operations eg data frame formatting preamble generation data transmission and appending CRC information without furt...

Page 54: ...d in the ASIF Timers and Baud Rate Generators The CPM incorporates four 16 bit timers that may be concatenated to form two 32 bit timers These timers can be used for general purpose timing when clocke...

Page 55: ...Interface on page 79 This frees the software from having to regularly poll these input lines 5 2 7 Communications Processor Interfaces In the ASIF the serial interface functions provided by the CPM a...

Page 56: ...double buffering is provided This requires that the data transfers from the SMC s registers be handled on a character by character basis by the CPM rather than in larger blocks of characters The SMC...

Page 57: ...SMC Conversely the TSA routes the transmit data output from the SMC and inserts the data stream into the selected time slot s in the frame The transmit data outputs of the TSA and the DSPs are tri st...

Page 58: ...e to recover the received data The SIO port on the reciter RISC is not double buffered so it is a limiting factor on the achievable transmission rate The MPC s SPI port is capable of variable length t...

Page 59: ...ut signals on input port IPA 0 7 also connect to the PCMCIA interface input register see PCMCIA Interface on page 44 so an interrupt can be generated on a change of state on those pins Pins on port C...

Page 60: ...utput on page 73 PB23 O P General purpose digital output 7 RSSI Output on page 73 PC6 O P none PC7 O P none PC8 O P none PC9 O P Option link PC10 O P none PC11 O P none PC12 I P E lead input PC13 I P...

Page 61: ...a unique identifier code and an OTP protection area which can be used for product identification and software feature enabling See the data sheet reference 3 for details of the operation of this chip...

Page 62: ...SDRAM chips are paired to provide a 32 bit data bus to match the MPC s data bus width The MPC always reads and writes 32 bit words but individual bytes can be written by using the byte select lines B...

Page 63: ...alid address L low H high X don t care SDRAM Initialisation After power up the SDRAM chips must be initialized and set to their correct operating mode before being used Prior to setting the operating...

Page 64: ...burst access an SDRAM can read or write new data every clock cycle after the initial memory access The SDRAM burst size is set to four words to match the MPC RISC CPU internal cache line refill size...

Page 65: ...sing its periodic timer to determine the refresh interval 5 4 DSP 5 4 1 DSP A TMS320VC5510 digital signal processor chip is provided for the vocoder and other signal processing functions It is a high...

Page 66: ...ied 32 bit data bus and 22 bit address bus ie a von Neumann type architecture Figure 5 7 DSP Block Diagram EHPI DMA Controller CPU Instruction Buffer Unit IU Program Flow Unit PU Address Data Flow Uni...

Page 67: ...utput The MPC can also interrupt the DSP using an internal interrupt register in the host port interface see Host Port Interface HPI on page 69 The MPC controls the DSP reset line via a parallel outpu...

Page 68: ...s RAM DARAM and 32 blocks totalling 128k half words of single access RAM SARAM Each type of internal memory can be accessed in a single clock cycle ie zero wait states With DARAM the DSP core can make...

Page 69: ...pleted loading the DSP code it sets this bit in the HPI control register signaling the DSP to jump to the start location and execute the loaded program 5 4 2 Host Port Interface HPI The DSP is connect...

Page 70: ...it until the data is fetched from the DSP memory by the DMA controller before the MPC memory cycle can be completed The MPC memory controller inserts wait states until the DSP indicates that the memor...

Page 71: ...EC chip is a client device McBSP0 is configured as a server device ie it generates the clocks and sync signals for the CODEC The CODEC does not require separate transmit and receive clocks so a clock...

Page 72: ...debouncing The filtered output passes through inverting Schmitt trigger U602 which squares up the signal and converts it to the LVTTL levels required by the MPC U602 has LVTTL compatible input thresho...

Page 73: ...incandescent lamps their size should be limited such that the initial turn on current does not exceed 250mA to avoid overstressing the output transistor The relay driver is controlled by parallel out...

Page 74: ...d by U700 a 10 100Mbps ethernet transceiver with twisted pair interface This device and the FEC are both capable of operating at either 10Mbps or 100Mbps half or full duplex and may use auto negotiati...

Page 75: ...registers As an alternative to SMI configuration some of the PHY register settings can be made through strapping external pins the state of these pins is sensed on the rising edge of RST and latched i...

Page 76: ...sfer to from the FEC occurs over separate receive and transmit buses each four bits wide and are clocked by RXCLK and TXCLK respectively supplied from the PHY On reception of a valid signal on the rec...

Page 77: ...he analog interface Data received from the DSP is processed by the CODEC to become an analog output The description below uses the same direction convention CODEC Transmit Operation Considering first...

Page 78: ...zed output resistance enables a greater output swing from a given power supply voltage than is possible using a real output resistor the amplifier is capable of driving in excess of 6dBm to a 600 line...

Page 79: ...KX0 since this is a steady 2 048MHz it is also used for the server clock input MCLK to the CODEC for its internal timing To synchronize the bit streams the CODEC also requires a frame synchronization...

Page 80: ...ng input PC12 of the MPC low This input is also paralleled with an interrupt input IRQ6 for rapid software response from the MPC As the E lead can be sourced from a wide range of voltages it is necess...

Page 81: ...r 12 8MHz clock is used as the DSP PLL s reference the clock signal DSP_CLK_IN from the reciter is buffered by U801 This is then passed to the DSP reference clock input DSP_ CLK via damping resistor R...

Page 82: ...910 to close the control loop These resistors are proportioned to provide 0 8V the internal reference voltage when the output voltage is 3 3V Since U900 uses a current mode control strategy the sensed...

Page 83: ...rrent directly from the auxiliary supply Since the internal linear regulator no longer wastes power dropping the 28V input down to 7 5V the overall power supply efficiency is increased providing that...

Page 84: ...ce minimize stresses on the power components During start up the output of the error amplifier is also clamped by the soft start circuit so that the allowable inductor current rises slowly minimizing...

Page 85: ...is a potential for damage to occur through chip latch up when the second board powers up In order to coordinate the power up sequence between the ASIF and the reciter digital board a hardware handsha...

Page 86: ...86 Network Circuitry TB9100 Reciter Service Manual Tait Electronics Limited January 2006...

Page 87: ...17dBm local oscillator mixer The voltage controlled oscillator VCO generates a level of 20dBm which is fed to the mixer through an attenuator pad A diplexer terminates the IF port of the mixer in 50 t...

Page 88: ...VCO feedback signal fvcofb and the reference oscillator fref The VCO feedback attenuator is a resistive divider that terminates the VCO feedback signal in a fixed low impedance 50 This attenuates the...

Page 89: ...justing the trimmer Changes in the control voltage from the loop filter are applied to the varactors to facilitate electronic tuning Low Noise Amplifier A BJT cascode amplifier is used as a broad band...

Page 90: ...Receiver VCO Programmable Reference Divider Programmable VCO Divider Phase Detector Lock Detect Output Charge Pump f ref f VCOfb Software Register VCO Feedback Attenuator Lock Detect Circuitry 64 65...

Page 91: ...mixer 6 2 2 Mixer The RF signal from the front end is converted down to the 70 1MHz IF by a high level 17dBm local oscillator mixer The voltage controlled oscillator VCO generates a level of 20dBM whi...

Page 92: ...ed low impedance 50 This attenuates the VCO RF level down to a level suitable for the RF prescaler within the synthesizer IC A 12 8MHz temperature controlled crystal oscillator TCXO is used as the int...

Page 93: ...utput provides enough RF power to drive the following stages Harmonic Filter The VCO has a high second harmonic content A third order low pass elliptic filter is used to attenuate this content Fixed S...

Page 94: ...Oscillators Modulation to the FCL_VCXO reference oscillator requires the use of the FCL_VCXO_CTRL and SYN_VCO_MOD signals to apply a constant DC offset to the FCL_VCXO signal until it achieves frequen...

Page 95: ...75dB FCL Processor and DAC The FCL processor runs a DSP based algorithm which takes the digitized signals I_Q and transmit audio and compares them to the transmit modulation calibration data Using the...

Page 96: ...on from the RISC processor via a 3 wire serial bus clock data and enable When the data bits are latched in the synthesizer processes the incoming signals from the VCO feedback signal fvcofb and the re...

Page 97: ...wisted Ring Counter Digital Clock Buffer Digital Clock Buffer 12 8MHz FCL VCXO Oscillator 12 8MHz Reference Oscillator VCXO Modulation DC Offset Exciter VCO Programmable Reference Divider Programmable...

Page 98: ...heir difference is zero or DC This is achieved by the phase detector part of the synthesizer IC which compares both divider references and delivers an error signal A 4mA charge pump circuit also part...

Page 99: ...ans from either 136MHz to 156MHz or 148MHz to 174MHz according to the product type 6 3 4 VCO UHF Reciter The exciter VCO consists of a high Q VCO modulation based on varicap diodes low noise amplifier...

Page 100: ...tenuator provides a signal level of 11dBm 2dB to the input port of the PA providing better reverse isolation The H band VCO frequency spans from either 400MHz to 440MHz 440MHz to 480MHz or 470MHz to 5...

Page 101: ...nalog sections of the network PCB via the digital PCB The 5 3V supply is regulated to 3 3V to power the RF synthesizers The RF PCB has a charge pump converter that generates 23V from both the 5 3V and...

Page 102: ...wer Switch Power Switch Protection Circuit Linear 5V Regulator Dual SMPS Regulator Dual SMPS Regulator Comparators Fan Switch Filter Filter 5V Regulator Filter 5V Regulator Switch Filter 28V 28V 5 3V...

Page 103: ...al Appendices 103 Tait Electronics Limited January 2006 8 Appendices 8 1 Appendix A I2 C Device Addresses Table 8 1 I2 C Device Addresses Device I2 C Address Range U202 24C16 E2PROM 0xA0 0xAF U500 TLV...

Page 104: ...on 1 VFLS0 O P Flush buffer status 2 SRESET I O Soft reset 3 GND 4 DSCK I P Debug serial clock 5 GND 6 VFLS1 O P Flush buffer status 7 HRESET I O Hard reset 8 DSDI I P Debug serial data in 9 3V3 10 DS...

Page 105: ...19 HS_DIG_IN_1 O P Reciter digital input 20 HS_DIG_IN_2 O P Reciter digital input 21 SIO_CLK I P Serial expansion interface clock 22 SIO_TXD I P Serial expansion interface transmit data 23 SIO_RXD O...

Page 106: ...Signal Name Direction Function 1 Not used 2 GND 3 Not used 4 GND 5 Not used 6 GND 7 Not used 8 GND 9 DSP_DT2 I P DSP receive data 10 GND 11 DSP_TCLD2 I P DSP receive clock 12 GND 13 DSP_TFS2 I P DSP r...

Page 107: ...O P Serial comms O P 3 RS232_RXD I P Serial comms I P 4 DIG0_IN I P General purpose digital input 5 GND 6 DIG1_IN I P General purpose digital input 7 DIG2_IN I P General purpose digital input 8 DIG3_I...

Page 108: ...Ta O P 4W audio output 4 Tb O P 4W audio output 5 Ra I P 4W audio input 6 Rb I P 4W audio input 7 Ma O P Signaling output 8 Mb O P Signalling output Table 8 8 DSP JTAG Connector Pinout Pin Number Sign...

Page 109: ...TP209 A2 CPU address type output AT0 TB210 A3 Flash memory chip select TP211 A3 SDRAM memory chip select TP212 A4 SDRAM write enable TP213 C6 Memory clock TP214 A3 SDRAM column address strobe TP215 A5...

Page 110: ...2 DSP serial port transmit clock TP409 E2 DSP serial port receive frame sync TP410 E2 DSP serial port receive clock TP411 F3 DSP serial port receive data TP412 E5 DSP clock output TP413 D2 DSP host po...

Page 111: ...ty these are not shown on the schematic Table 8 10 MPC859T Port Assignments Pin Name Pin No Type Function A 0 B19 I O Address bus 0 msb A 1 B18 I O Address bus 1 A 2 A18 I O Address bus 2 A 3 C16 I O...

Page 112: ...lect BB E1 I O Bus Busy BDIP GPL_B5 D2 O P Burst Data In Progress General purpose Line B5 BG E2 I O Bus Grant BI E3 I O Burst Inhibit BR G4 I O Bus Request BRGO1 I2CSDA PB27 E19 I O BRG1 output clock...

Page 113: ...5 CS6 CE1B D5 O P Chip Select 6 Card Enable 1 Slot B CS7 CE2B C4 O P Chip Select 7 Card Enable 2 Slot B CTS1 PC11 J19 I O Clear to send modem line for SCC1 General purpose I O port C bit 11 D 0 W14 I...

Page 114: ...sb DPO IRQ3 V3 I O Data Parity 0 Interrupt Request 3 DP1 IRQ4 V5 I O Data Parity 1 Interrupt Request 4 DP2 IRQ5 W2 I O Data Parity 2 Interrupt Request 5 DP3 IRQ6 V4 I O Data Parity 3 Interrupt Request...

Page 115: ...A 4 MII Receive Clock UTOPIA Split Bus 4 IPA5 MIIRXERR UTPB_Split 5 U5 I P Input Port A 5 MII Receive Error UTOPIA Split Bus 5 IPA6 MIITXERR UTPB_Split 6 T6 I O Input Port A 6 MII Transmit Error UTOP...

Page 116: ...T17 I O Receive sync input for serial interface TDMa General purpose I O port C bit 4 L1RxDA PA8 L17 I O Receive data input for the serial interface TDMa General purpose I O Port A bit 8 L1RxDB PA10...

Page 117: ...ata O P for the serial interface TDMa General purpose I O Port A bit 9 L1TxDB PA11 G16 I O Transmit data O P for serial interface TDMb General purpose I O port A bit 11 MII_MDIO H18 I O MII management...

Page 118: ...dependent interface transmit data 2 General purpose I O Port D Bit 4 UTOPIA bus bit 7 input output signal most significant bit of UTPB MIITXD3 PD5 UTPB 6 U15 I O Media independent interface transmit d...

Page 119: ...0 TXADDR0 L16 I O SMC2 receive data input Clock output from the serial interface TDMa General purpose I O port B bit 20 Most significant bit of PHY select bus UTOPIA multi PHY transmit address line 0...

Page 120: ...BRGO2 CLK3 PA5 N18 I O Timer 2 external clock input Transmit clock for the serial interface TDMa Output clock of BRG2 Clock inputs for SCCs and SMCs General purpose I O port A bit 5 TIN3 BRGO3 CLK5 P...

Page 121: ...VSSSYN PWR PLL ground VSSSYN1 PWR PLL ground WAITA SOC_Split R3 I P Wait Slot A Start of Cell in UTOPIA Split Bus Mode WAITB R4 I P Wait Slot B WE0 BS_B0 IORD C7 O P Write Enable 0 Byte Select 0 on U...

Page 122: ...8 A 9 A2 O P External memory address bus 9 A 10 C1 O P External memory address bus 10 A 11 E1 O P External memory address bus 11 A 12 F3 O P External memory address bus 12 A 13 F2 O P External memory...

Page 123: ...Ext clock source to the sample rate generator 1 CLKS2 P8 I P Ext clock source to the sample rate generator 2 CLKX0 U7 I O Serial shift clock input for McBSP 0 CLKX1 R15 I O Serial shift clock input fo...

Page 124: ...O External data bus 31 DR0 T6 I P Serial receive data input for McBSP 0 DR1 P3 I P Serial receive data input for McBSP 1 DR2 R7 I P Serial receive data input for McBSP 2 DVDD PWR Dedicated power suppl...

Page 125: ...HA 13 G17 I P Host address bus 13 HA 14 H16 I P Host address bus 14 HA 15 J15 I P Host address bus 15 HA 16 K16 I P Host address bus 16 HA 17 M15 I P Host address bus 17 HA 18 M14 I P Host address bu...

Page 126: ...P Maskable external interrupt 1 INT2 R13 I P Maskable external interrupt 2 INT3 T14 I P Maskable external interrupt 3 INT4 P12 I P Maskable external interrupt 4 INT5 R11 I P Maskable external interru...

Page 127: ...nable TCK L17 I P IEEE Standard 1149 1 test clock TDI L16 I P IEEE Standard 1149 1 test data input TDO L16 O P IEEE Standard 1149 1 test data output TIN TOUT0 P15 I O Timer 0 input output TIN TOUT1 R1...

Page 128: ...02 M8 1H3 C606 E2 6F3 C915 L5 9G7 C103 M8 1F3 C607 D2 6F3 C916 N7 9E7 C104 H7 1B3 C608 D2 6E3 C917 M6 9H7 C105 M8 1H3 C609 K5 6D3 C918 L7 9F9 C106 N8 1E3 C615 N4 6E7 C919 H5 9D10 C107 N8 1F3 C619 N4 6...

Page 129: ...3 Q910 L7 9B12 D700 G3 7F9 E602 C2 6G3 R100 K6 1E2 D900 M5 9G5 9G7 E603 E2 6G3 R101 N8 1H4 D901 H7 9F12 E604 D2 6F3 R102 G7 1C13 D902 H7 9E12 9F12 E605 D2 6E3 R110 L8 1H4 D903 J8 9C12 E606 K5 6D3 R111...

Page 130: ...E112 N7 1F5 Q500 L3 5H10 R220 A4 2F7 2C10 2C9 E500 N3 5F2 Q501 K6 6C6 R221 A5 2F7 2G7 2C10 2D10 E501 H2 5K12 Q501 K6 5J7 R222 C6 2H2 E502 H2 5J12 Q503 K3 5H9 R223 D3 2G11 E503 H2 5J12 Q504 K4 5G10 5H...

Page 131: ...E5 R706 F3 7F10 TP204 A4 2C1 R512 L4 5H9 R708 F4 7D7 TP205 A6 2C1 R513 L4 5H9 R708 F4 4C8 TP206 A7 2H1 R514 L3 5G9 R710 G3 7F10 TP207 A3 2D1 R515 L4 5G10 R711 G3 7F10 TP208 A6 2D1 R516 P2 5E7 R712 F3...

Page 132: ...3 4E8 U210 D4 2J12 2D14 U800 G5 8A6 8E6 TP407 D3 4E8 U211 D4 2D13 2J12 U801 F3 8D6 8A7 TP408 E3 4D8 U212 D3 2G11 2B14 U900 N6 9F6 TP409 E3 4E8 U213 D3 2G11 2D14 U901 K8 9C8 TP410 E3 4D8 U300 B7 3D6 U9...

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Summary of Contents for TB9100

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Tait TB9100, Service Manual, Page: 117 / 132

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Summary of Contents for TB9100

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