Tait TB9100, Service Manual, Page: 42 / 132

42 Network Circuitry TB9100 Reciter Service Manual
© Tait Electronics Limited January 2006
The MPC also supports JTAG mode for board testing, but this is not
implemented on the ASIF due to lack of space for another connector.
Basically, a JTAG port provides access to all the MPC’s pins so that checks
may be made for continuity, shorts, etc. Unlike the DSP (see
“Processor
Core” on page 66 ), the JTAG port is not used for program debugging on
the MPC.
5.2.2 System Interface Unit (SIU)
The SIU ties together the MPC’s internal and external bus interfaces and
provides ancillary services to the RISC core. These include clock
generation, timer functions, system configuration, interrupt control and the
PCMCIA interface.
Clock Generation
To achieve high performance the MPC requires a high-frequency clock.
This high-frequency clock is generated internally to the MPC by
multiplying up a relatively low-frequency reference clock input, using an
internal phase-locked loop (PLL) to minimize EMC problems. The input
reference clock (EXTCLK) can be multiplied by various ratios with the
proviso that the final PLL operating frequency must lie in the range
160MHz to 266MHz.
The CPU clock defaults to the PLL clock divided by 2, although higher
division ratios are available where it is desired to run the CPU at a lower
clock frequency to save power. Other clocks for peripheral circuitry are
derived by independent dividers from the PLL clock so that the peripheral
clocks remain constant, even if the CPU clock is reduced for lower power
operation.
The multiplication ratio from reference frequency to PLL frequency is set
by programming several PLL registers to give multipliers that are a ratio of
two integers. In the ASIF, these registers are set for an overall multiplication
ratio of 9 8/13, giving an MPC clock of 125MHz from the 13MHz
reference clock (see
“Clock Oscillator” on page 81 ).
Prior to the program running and being able to set up the PLL registers,
default values are loaded into these registers to enable MPC operation.
The default values are determined by the MODCK[0..1] inputs (see
“MPC
Reset” on page 44 and Table 5.3 ). Once the MPC program is up and
running, it reprograms the PLL registers to their final values.
Time Bases and
Watchdog
The PowerPC architecture includes several supplementary timer functions
to provide hardware and software monitoring and operating system support:
■
Bus monitor
■
Software watchdog timer
■
Periodic Interrupt Timer
■
Time base counter
■
Decrementer