Tait TB9100, Service Manual, Page: 70 / 132

70 Network Circuitry TB9100 Reciter Service Manual
© Tait Electronics Limited January 2006
The HPI has two modes of operation: multiplexed and non-multiplexed
address/data; the ASIF uses non-multiplexed mode as selected by the
HMODE pin. In non-multiplexed mode, the host port appears to be a
single large window into the DSP memory space. Actually, only two 16-bit
registers exist in the DSP, the data register HPID and the control register
HPIC; the transfer of data to and from the DSP memory takes place under
control of the internal DMA controller. This gives the appearance, to the
host processor, of the entire DSP memory space being accessible, albeit with
some delay due to the need for the DMA controller to gain access to the
internal memory.
For a write operation to the HPI, the MPC places the desired address on the
host port address bus, HA[0..19], and data to be written on the host port
data bus, HD[0..15]. The HCNTL line, connected to address line A20, is
set high to indicate an access to the data register. The host port chip select
(HCS), read/write (HR_W) and write data strobes (HDS2) are activated as
appropriate. This latches the data into the HPID register, which acts as a
temporary holding register. From there, the DMA controller in the DSP
transfers the data to the correct location in DSP memory, as determined by
the address on HA[0..19].
A read operation from the HPI follows the same sequence, except that the
MPC must wait until the data is fetched from the DSP memory, by the
DMA controller, before the MPC memory cycle can be completed.
The MPC memory controller inserts wait states until the DSP indicates that
the memory cycle can be completed by taking its HRDY output high.
This is connected through to the MPC’s TA input (see “MPC Bus Cycles”
on page 48 ), via flip-flop U204 and tri-state buffer U212, to terminate the
bus cycle. U212 is controlled by flip-flop U204 to ensure the TA timing is
synchronized to the MPC’s memory clock. When the DSP is not selected,
it outputs its HRDY signal as high, ie. a false HRDY signal. To prevent this
false HRDY signal prematurely terminating a DSP access cycle or other
non-DSP bus cycles, flip-flop U204 is inhibited from clocking, by gate
U213, when the DSP chip select, HCS, is inactive.
Shortly after the DSP chip select, CS2, is asserted, it continues to output a
false HRDY signal until its internal logic recognizes the HCS input and
outputs the correct HRDY state. To prevent this delayed HRDY response
generating a TA, prematurely terminating the bus cycle, gate U213
continues to inhibit flip-flop U204 from clocking for approximately 150ns
after HCS has been asserted. The delay is provided by RC network R223
and C210, while diode D201 and resistor R225 ensure that the delay circuit
quickly recovers in time for the next cycle. A direct, undelayed path through
the other input of U213 ensures the flip-flop U204 is reset, and TA negated,
immediately after HCS has been negated.
Note
U204, U212 and U213 are omitted from current network boards.
The MPC performs a wait following each write cycle to DSP
memory.