TB9100 Reciter Service Manual
Network Circuitry
33
© Tait Electronics Limited January 2006
5
Network Circuitry
5.1
Top Level Block Diagram
A simplified block diagram of the ASIF is shown in
Figure 5.1
. The top-
level schematic sheet (226-02056-01 sheet 1) shows a more detailed view of
the main circuit blocks together with their interconnections and external
connections to/from the ASIF board.
There are seven main circuit blocks:
■
RISC processor
■
DSP
■
I/O buffers
■
ethernet interface
■
audio and E&M interface
■
clock oscillator
■
power supply
The RISC processor block (see
“Risc Processor” on page 38
) is the heart of
the ASIF, providing the main control functions and most of the peripheral
interface functions. This block also contains the main memory for the ASIF
(see
“Memory” on page 61
), all of which is interfaced to the RISC
processor. From the RISC processor block various signals are routed to the
reciter via connector J101 whilst other signals are routed through the I/O
buffers, the ethernet interface and the audio and E&M interface blocks to
connect to the outside world.
These interfaces provide signal formatting, signal level conversion, I/O
protection, etc, for the logic level signals emanating from the RISC
processor. The I/O buffers block (see
“I/O Buffers” on page 71
) mainly
handles general-purpose digital I/O to/from the RISC processor along with
level conversion for an RS-232 port. Also included in this block is an analog
amplifier for amplifying/buffering the RSSI output. The interface acts as a
conduit for the RSSI signal from the reciter, as the ASIF does not use this
signal in any way.
The ethernet interface (see
“Ethernet Interface” on page 74
) contains an
ethernet PHY chip together with line interface components. The PHY
chip incorporates logic to format the ethernet signals from the RISC
processor to a suitable format for line transmission. It also includes line
drivers and receivers to convert the twisted pair ethernet signals to logic
levels.
The audio and E&M interface (see
“Audio and E&M Interface” on page 77
)
is jointly controlled by the RISC processor and the DSP. The E&M
signalling is connected to the RISC processor. Audio data to/from the DSP
Summary of Contents for TB9100
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