Supero X8DTH-6, User Manual

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Chapter 1: Introduction
1-9
1-2 Chipset Overview
Built upon the functionality and the capability of the Intel 5500 Series Processor
and the 5520 chipset, the X8DTH-6/X8DTH-6F/X8DTH-i/X8DTH-iF motherboard
provides the performance and feature set required for dual-processor-based
high-end systems optimized for High Performance Computing (HPC)/Clustering
severs. The Intel 5520 chipset consists of dual 5520 IO hubs, and an ICH10R
(South Bridge). With the Intel QuickPath Interconnect (QPI) controller built in, the
Intel 5500 Series Processor is the fi rst dual-processing platform to offer the next
generation point-to-point system interconnect interface to replace the current
Front Side Bus Technology, substantially enhancing system performance and
scalability.
The 5520 IO Hub connects to each processor through an independent QPI link.
Each link consists of 20 pairs of unidirectional differential lanes for transmission
and receiving in addition to a differential forwarded clock. A full-width QPI link
pair provides 84 signals.
The Intel 5520 supports up to 36 PCI Express Gen2 lanes, peer-to-peer read and
write transactions. The ICH10R provides up to seven PCI-Express ports, six SATA
ports and seven USB connections.
In addition, the Intel 5520 chipset also offers a wide range of RAS (Reliability,
Availability and Serviceability) features. These features include memory interface
ECC, x4/x8 Single Device Data Correction (SDDC), Cyclic Redundancy Check
(CRC), parity protection, out-of-band register access via SMBus, memory mirror-
ing, and Hot-plug support on the PCI-Express Interface.
Main Features of the 5500 Series Processor and the 5520
Chipset
Four processor cores in each processor with 8MB shared cache among cores
•
Two full-width Intel QPI links, up to 6.4 GT/s of data transfer rate in each direc-
•
tion
Virtualization Technology, Integrated Management Engine supported
•
Point-to-point cache coherent interconnect, Fast/narrow unidirectional links, and
•
Concurrent bi-directional traffi c
Error detection via CRC and Error correction via Link level retry
•