Supero SuperWorkstation 5035G-T, User Manual

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UPER
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ORKSTATION 5035G-T User's Manual
1-2 Motherboard Features
At the heart of the SuperWorkstation 5035G-T lies the PDSGE, a single processor
motherboard. Below are the main features of the PDSGE.
Chipset Overview
The PDSGE is based on Intel’s 955X chipset. See Figure 1-1 for a block diagram
of the chipset. The 955X chipset is made up of two main components:
The Memory Controller Hub (MCH)
The I/O Controller Hub (6300ESB)
Memory Controller Hub (MCH)
The MCH includes the host (CPU) interface, memory interface, I/O controller hub in-
terface, CSA interface and AGP interface. It contains advanced power management
logic and supports dual-channel (interleaved) DDR memory, providing bandwidth of
up to 6.4 GB/s using DDR-400 SDRAM. The MCH supports the following front side
bus/memory bus confi gurations: 800 MHz FSB with a 400/333 memory interface, a
533 MHz FSB with a 333/266 memory interface and a 400 MHz FSB with a 266 MHz
memory interface. The AGP interface supports 8x data transfers and operates at a
peak bandwidth of 2.1 GB/s. The CSA (Communications Streaming Architecture)
interface connects the MCH to a Gigabit Ethernet controller.
I/O Controller Hub (6300ESB)
The 6300ESB ICH controller hub provides the I/O subsystem with access to the rest
of the system. It integrates two Serial ATA (SATA) host controllers, a dual-channel
Ultra ATA/100 bus master IDE controller, an SMBus 2.0 controller, the LPC/Flash
BIOS interface, the PCI-X (66MHz) 1.0 interface, the PCI 2.2 interface and the System
Management Controller.