Supermicro X6DA3-G2, User Manual

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X6DA3-G2/X6DAi-G2 User's Manual
Advanced Chipset Control
Access the submenu to make changes to the following settings.
Force Compliance Mode Entry
If enabled, this feature sets the device specifi ed to comply with the PCI-Express
Compliance 1.0 Mode. The options are: Disabled and Enabled.
Memory RAS Feature Control
Select this option to enable Memory RAS (Reliability/ Availability/Serviceability)
Feature Control. The Options are Standard , Sparing, and Mirroring. Select Sparing
(RAID 0) to increase the performance of data transfer by simultaneously writing
data to two drives. Select Mirroring (RAID 1) to increase data protection by writing
identical data on two drives.
Clock Spectrum Feature
If "Enabled", BIOS will sensor and attempt to reduce the Electromagnetic Interference
caused by the components. The options are Enabled and Disabled .
Memory Remap Function Control
PCI memory resources will overlap with the physical memory if 4GB of memory or
above is installed on the motherboard. When this occurs, enable this function to
reallocate the overlapped physical memory to a location above 4GB to resolve the
memory overlapping situation.
Delayed Transaction Discard
Select Disabled to set the ESB P2P Bridge Secondary Discard Timer to 32 micro-
seconds for the PCI-32 bus. Select Enabled to set the ESB P2P Bridge Secondary
Discard Timer to 4 micro-seconds for the PCI-32 bus.
DRAM Data Integrity Mode
If enabled, this feature allows the data stored in the DRMA memory to be integrated
for faster data processing. The options are 72-bit ECC, 144-bit ECC, Auto and
Disabled.
ECC Error Type
This setting lets you select which type of interrupt to be activated as a result of an
ECC error. The options are None, NMI (Non-Maskable Interrupt), SMI (System
Management Interrupt) and SCI (System Control Interrupt.)
SERR (System Error) Signal Condition
This setting specifi es the conditions required to be qualifi ed as an ECC error. The
options are None, Single Bit , Multiple Bit and Both.