Super X8SI6-F, User Manual

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4-12
X8SIE/X8SIE-F/X8SI6-F/X8SIE-LN4/X8SIE-LN4F
PCI Latency Timer
This feature sets the latency Timer of each PCI device installed on a PCI bus. Select
64 to set the PCI latency to 64 PCI clock cycles. The options are 32,
64 , 96, 128,
160, 192, 224 and 248.
PCI IDE Bus Master
When enabled, the BIOS uses PCI bus mastering for reading/writing to IDE drives.
The options are
Disabled and Default.
PCIE I/O Performace
This feature selects the setting for the IOH PCIE maximum payload size. The op-
tions are
128B and 256B .
ROM Scan Ordering
This item determines what kind of option ROM activates over another. The options
are
Onboard First and Add-on First.
PCI Slot 1, PCIe Slot 2 & 6 OPROM
Use this feature to enable or disable PCI slot Option ROMs. The options are Dis-
abled and
Enabled.
Onboard LAN1 Option ROM Select
Use this feature to select which boot option ROM to load for LAN1. The options
are
PXE
and iSCSI.
Load Onboard LAN1 Option ROM
Load Onboard LAN2 Option ROM
Load Onboard LAN3 Option ROM (X8SIE-LN4 only)
Load Onboard LAN4 Option ROM (X8SIE-LN4 only)
This feature is to enable or disable the onboard LAN option ROMs. The options
are
Disabled and Enabled.
Boot Graphics Adapter Priority
Use this feature to select the graphics controller to be used as the primary boot
device. The options are Other,
Onboard VGA
and Slot 6. Select Slot 6 if a graphics
controller is installed in the CPU-controlled Slot 6 slot.

Super IO Device Configuration
Serial Port1 Address/ Serial Port2 Address
This option specifies the base I/O port address and the Interrupt Request address
of Serial Port 1 and Serial Port 2. Select Disabled to prevent the serial port from