Sun Microsystems SunSwift SPARCserver 1000, Service Manual

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Glossary-6 SPARCserver 1000 System Service Manual—June 1996
MXCC (Module XBus Cache Controller)
The MXCC ASIC is located on the processor module and controls flow of data
between the XBus and the module cache RAM and processor chip.
NVSIMM
The nonvolatile SIMM (NVSIMM) design incorporates a battery on the device
to prevent data loss in the event of power failure. Battery current is shared
among a group of NVSIMMs. This feature prevents memory failure should one
battery fail.
Power-on Reset
Reset signals produced by reset circuitry on the control board. At power-on,
reset is asserted for 200msec and is distributed to each system board to
initialize all ASICs. The reset PAL maintains system reset until Vtt is ready.
Processor
See SuperSPARC Module.
Processor Bus
Found only on the SuperSPARC module. To compare bus types, see Bus.
Replaceable Unit
Replaceable units are server subassemblies which can be replaced at the
customer site by trained, qualified service personnel.
XDBus
BW BW
Processor
XBus
R
A
M
MXCC