SIS Documentation
SIS3820
VME Scaler
Page 63 of 79
13 TTL output configuration
Standard TTL units drive high impedance signals (i.e. 24 mA current), a 50
Ω
driver piggy
(driving 48 mA) pack is installed on 50
Ω
TTL units. It plugs into the socket U170 instead of
the standard driver chip.
14 Signal Specification
14.1 Control Signals
The width of clear and external next pulses has to be greater or equal 10 ns, an external inhibit
(disable counting) has to be present for the period you desire to disable counting. An internal
delay of some 15 ns has to be taken into account for all external signals.
14.2 Inputs
The SIS3820 is specified for counting rates of 250 MHz for ECL and NIM signals and 100
MHz for the TTL case. Thus the minimum high and low level duration is 2.0 ns (5 ns
respective). Signal deterioration over long cables has to be taken into account.
14.3 User Bits
The status of the user bits is latched with the leading edge of the external LNE pulse. A setup
time of greater equal 10 ns and a hold time of 25 ns is required, i.e. the signal should have a
length of greater 35 ns and has to be valid 10 ns before the leading edge of the LNE pulse
arrives. User bit information is pipelined, i.e. the information that is stored with the scaler
values was recorded at the beginning of the counting period.