SIS Documentation
SIS3820
VME Scaler
Page 58 of 79
11.3 JP570 JTAG source
Firmware can be loaded to the XC18V04 serial PROM via a JTAG download cable (XILINX
JTAG-PC4 e.g.) or via the VME interface of the SIS3830. Please note, that errors during this
process can render a module temporarily in non working condition.. JP570 has 3 pins.
Depending on whether pins 1 and 2 or 2 and 3 are closed the JTAG source is defined as listed
below.
Closed JTAG
source
1-2
JTAG connector CON 500
2-3 VME
Note:
shipping default is 1-2 closed (i.e. JTAG over CON500)
11.4 CON500 JTAG
The SIS3820 on board logic can load its firmware from a serial PROMs . The firmware can
be upgraded through VME (future option) or the JTAG connector. A list of firmware designs
can be found under http://www.struck.de/sis3820firm.htm.
Hardware like the XILINX HW-JTAG-PC in connection with the appropriate software (the
XILINX WebPACK is furnished on the accompanying CDROM) will be required for in field
JTAG firmware upgrades through the JTAG connector.
The JTAG connector is a 9 pin single row 1/10 inch header, the pin assignment on the
connector can be found in the table below.
Pin Short
hand
Description
1 VCC Supply
voltage
2 GND Ground
3
nc
not connected, cut to avoid polarity mismatch
4 TCK test
clock
5 nc
not
connected
6
TDO
test data out
7 TDI test
data
in
8
nc
not connected
9 TMS test
modus
Note:
close the J90 disable watchdog jumper for firmware upgrades