SIS Documentation
SIS3820
VME Scaler
Page 19 of 79
7.1 Control/Status
Register(0x,
write/read)
#define SIS3820_CONTROL_STATUS
0x0
/* read/write; D32 */
The control register is in charge of the control of some basic properties of the SIS3820 board,
like enabling test pulse generators. It is implemented via a selective J/K register, a specific
function is enabled by writing a 1 into the set/enable bit, the function is disabled by writing a
1 into the clear/disable bit (which location is 16-bit higher in the register). An undefined
toggle status will result from setting both the enable and disable bits for a specific function at
the same time.
On read access the same register represents the status register.
Bit
write Function
read Function
31
Status external LATCH Bit2 (depending on
Input Mode)
30
Status external LATCH Bit1 (depending on
Input Mode)
29
Status external Input Bit2 (depending on
Input Mode)
28
Status external Input Bit1 (depending on
Input Mode)
27
Overflow
26
0
25
Status HISCAL operation enable
24
Status
Operation
armed
23
Status Operation SDRAM/FIFO Test
enabled
22
switch off reference pulser channel 1 (*)
0
21
counter test mode (*)
0
20
clear 25MHz test pulses (*)
0
19
0
18
Status Operation MCS enable (active)
17
0
16
switch off user LED (*)
Status Operation Scaler enable (active)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
switch on 50 MHz reference pulser channel 1 Status reference pulser
5
enable counter test mode
Status counter test mode enable
4
enable 25MHz test pulses
Status 25MHz test pulses
3
0
2
0
1
0
0
switch on user LED
Status User LED (1=LED on, 0=LED off)
(*) denotes power up default setting, i.e. the power up reading of the register is 0x0
