Hardware layout and configuration
UM1855
42/100
DocID027351 Rev 3
potentiometer or LDR to PA0, en external source can also be connected to it, using the
terminal 1 of JP7.
The PA3 output of the operational amplifier can be accessed on test point TP9. Refer to the
schematic diagram in
Figure 46
.
The gain of OpAmp1 is determined by the ratio of the variable resistor RV2 and the resistor
R121, as shown in the following equation:
With the RV2 ranging from 0 to 10 k
Ω
and R121 being 1 k
Ω
, the gain can vary from 1 to 11.
The R63 resistor in series with PA0 is beneficial for reducing the output offset.
2.19.2 Comparator
STM32L476ZGT6 provides two on-board comparators, one of which, Comp2, is made
accessible on STM32L476G-EVAL. Comp2 has its non-inverting input and its output routed
to I/O ports PB4 and PB5, respectively. The input is accessible on the terminal 3 of the JP7
jumper header. On top of the possibility of routing either of the potentiometer or LDR to PB4,
en external source can also be connected to it, using the terminal 3 of JP7.
The PB5 output of the comparator can be accessed on test point TP6. Refer to the
schematic diagram in
Figure 46
.
2.20
Analog input, output, VREF
STM32L476ZGT6 provides on-board analog-to-digital converter, ADC and, digital-to-analog
converter, DAC. The port PA4 can be configured to operate either as ADC input or as DAC
output. PA4 is routed to the two-way header CN8 allowing to fetch signals to or from PA4 or
to ground it by fitting a jumper into CN8.
Parameters of the ADC input low-pass filter formed with R72 and C47 can be modified by
replacing these components according to application requirements. Similarly, parameters of
the DAC output low-pass filter formed with R73 and C47 can be modified by replacing these
components according to application requirements.
The VREF+ terminal of STM32L476ZGT6 is used as reference voltage for both ADC and
DAC. By default, it is routed to VDDA through a jumper fitted into the two-way header CN10.
The jumper can be removed and an external voltage applied to the terminal 1 of CN10, for
specific purposes.
2.21 SRAM
device
IS61WV102416BLL, a 16-Mbit
static RAM (SRAM)
,
1 M x16 bit,
is fitted on the
STM32L476G-EVAL main board, in U2 position. The STM32L476G-EVAL main board as
well as the addressing capabilities of FMC allow hosting SRAM devices up to 64 Mbytes.
This is the reason why the schematic diagram in
Figure 41
mentions several SRAM
devices.
The SRAM device is attached to the 16-bit data bus and accessed with FMC. The base
address is 0x6000 0000, corresponding to NOR/SRAM1 bank1. The SRAM device is
Gain
1
RV2
(
)
R121
(
)
÷
+
=