Hardware layout and configuration
UM1855
34/100
DocID027351 Rev 3
Figure 10. LCD glass module daughterboard in I/O-bridge position
Table 14. LCD-daughterboard-related configuration elements
LCD
segment
Element
Setting to enable
LCD glass
module
Description
SEG0
R82
In
PA1 routed to LCDSEG0
SB32
Open
PA1 not routed to motor control
SEG1
R81
In
PA2 routed to LCDSEG1
SB31
Open
PA2 not routed to motor control
SEG2
R78
In
PA3 routed to LCDSEG2
SB22
Open
PA3 not routed to motor control
SEG3
R68
In
PA6 routed to LCDSEG3
SB21
Open
PA6 not routed to Quad-SPI Flash memory device
SB20
Open
PA6 not routed to motor control
SEG4
R66
In
PA7 routed to LCDSEG4
SB18
Open
PA7 not routed to Quad-SPI Flash memory device
SB19
Open
PA7 not routed to motor control
SEG5
R62
In
PB0 routed to LCDSEG5
SB14
Open
PB0 not routed to Quad-SPI Flash memory device
SB15
Open
PB0 not routed to motor control
SEG6
R56
In
PB1 routed to LCDSEG6
SB12
Open
PB1 not routed to Quad-SPI Flash memory device
SB13
Open
PB1 not routed to motor control
SEG10
R50
In
PB10 routed to LCDSEG10
SB9
Open
PB10 not routed to Quad-SPI Flash memory device
