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UM1855
Hardware layout and configuration
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The potentiometer and the light-dependent resistor can be routed, mutually exclusively, to
either PB4 or to PA0 port of STM32L476ZGT6.
Table 23
depicts the setting of associated
configuration jumpers.
As illustrated in the schematic diagram in
Figure 46
, the PB4 port is routed, in the
STM32L476ZGT6, to the non-inverting input of comparator Comp2. The PA0 is routed to
non-inverting input of operational amplifier OpAmp1. However, depending on register
settings, it can also be routed to ADC1 or to ADC2.
2.18.1 Limitations
The potentiometer and the light-dependent resistor are mutually exclusive.
2.19
Operational amplifier and comparator
2.19.1 Operational
amplifier
STM32L476ZGT6 provides two on-board operational amplifiers, one of which, OpAmp1, is
made accessible on STM32L476G-EVAL. OpAmp1 has its inputs and its output routed to
I/O ports PA0, PA1 and PA3, respectively. The non-inverting input PA0 is accessible on the
terminal 1 of the JP7 jumper header. On top of the possibility of routing either of the
Resistive touch screen Y-
Y-
IOExpander1
Potentiometer
PB4 or PA0
STM32L476ZGT6
LDR
PA0 or PB4
STM32L476ZGT6
Table 23. Setting of jumpers related with potentiometer and LDR
Jumper
Setting
Routing
JP5
JP7
JP5
JP7
Potentiometer is routed to pin PB4 of STM32L476ZGT6.
JP5
JP7
JP5
JP7
Default setting.
Potentiometer is routed to pin PA0 of STM32L476ZGT6.
JP5
JP7
JP5
JP7
LDR is routed to pin PB4 of STM32L476ZGT6.
JP5
JP7
JP5
JP7
LDR is routed to pin PA0 of STM32L476ZGT6.
Table 22. Port assignment for control of physical input devices (continued)
Input device
Control port
Control device
