STMicroelectronics STM32L162RC Page 97 Manual Download

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DocID022881 Rev 10

97/123

STM32L162VC, STM32L162RC

104

Figure 27. Maximum dynamic current consumption on V

REF+

supply pin during ADC

conversion

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 9

. The applicable

procedure depends on whether V

REF+

is connected to V

DDA

or not. The 100 nF capacitors

should be ceramic (good quality). They should be placed as close as possible to the chip.

ADC clock

Sampling (n cycles)

Conversion (12 cycles

)

ref+

300µA

700µA

MS36686V1

Table 58. Maximum source impedance R

AIN

max

(1)

(µs)

AIN

max (k

)

Ts (cycles)

ADC

=16 MHz

(2)

Multiplexed channels

Direct channels

2.4 V < V

DDA

< 3.6 V 1.8 V < V

DDA

< 2.4 V 2.4 V < V

DDA

< 3.6 V 1.8 V < V

DDA

< 2.4 V

0.25

Not allowed

0.7

Not allowed

0.5625

0.8

Not allowed

2.0

1.0

2.0

0.8

4.0

3.0

1.5

3.0

1.8

6.0

4.5

6.8

4.0

15.0

10.0

15.0

10.0

30.0

20.0

32.0

25.0

50.0

40.0

192

50.0

384

1. Guaranteed by design.

2. Number of samples calculated for f

ADC

= 16 MHz. For f

ADC

= 8 and 4 MHz the number of sampling cycles can be reduced

with respect to the minimum sampling time Ts (µs),

Summary of Contents for STM32L162RC

Page 1: ...USB 48 MHz Pre programmed bootloader USB and USART supported Development support Serial wire debug supported JTAG and trace supported Up to 83 fast I Os 70 I Os 5V tolerant all mappable on 16 external interrupt vectors Memories 256 KB Flash memory with ECC 32 KB RAM 8 KB of true EEPROM with ECC 128 byte backup register LCD Driver for up to 8 40 segments Support contrast adjustment Support blinking...

Page 2: ... 3 3 2 Power supply supervisor 18 3 3 3 Voltage regulator 19 3 3 4 Boot modes 19 3 4 Clock management 20 3 5 Low power real time clock and backup registers 22 3 6 GPIOs general purpose inputs outputs 22 3 7 Memories 23 3 8 DMA direct memory access 23 3 9 LCD liquid crystal display 24 3 10 ADC analog to digital converter 24 3 10 1 Temperature sensor 25 3 10 2 Internal voltage reference VREFINT 25 3...

Page 3: ... Universal serial bus USB 29 3 19 CRC cyclic redundancy check calculation unit 30 3 20 Development support 31 3 20 1 Serial wire JTAG debug port SWJ DP 31 3 20 2 Embedded Trace Macrocell 31 4 Pin descriptions 32 5 Memory mapping 46 6 Electrical characteristics 47 6 1 Parameter conditions 47 6 1 1 Minimum and maximum values 47 6 1 2 Typical values 47 6 1 3 Typical curves 47 6 1 4 Loading capacitor ...

Page 4: ...6 3 14 NRST pin characteristics 83 6 3 15 TIM timer characteristics 84 6 3 16 Communications interfaces 85 6 3 17 12 bit ADC characteristics 93 6 3 18 DAC electrical specifications 98 6 3 19 Operational amplifier characteristics 100 6 3 20 Temperature sensor characteristics 102 6 3 21 Comparator 102 6 3 22 LCD controller 104 7 Package information 105 7 1 LQFP100 14 x 14 mm 100 pin low profile quad...

Page 5: ...om RAM 57 Table 20 Current consumption in Sleep mode 58 Table 21 Current consumption in Low power run mode 59 Table 22 Current consumption in Low power sleep mode 60 Table 23 Typical and maximum current consumptions in Stop mode 61 Table 24 Typical and maximum current consumptions in Standby mode 63 Table 25 Peripheral current consumption 64 Table 26 Low power mode wakeup timings 66 Table 27 High ...

Page 6: ...able 60 Operational amplifier characteristics 100 Table 61 Temperature sensor calibration values 102 Table 62 Temperature sensor characteristics 102 Table 63 Comparator 1 characteristics 102 Table 64 Comparator 2 characteristics 103 Table 65 LCD controller characteristics 104 Table 66 LQPF100 14 x 14 mm 100 pin low profile quad flat package mechanical data 105 Table 67 LQFP64 10 x 10 mm 64 pin low...

Page 7: ...gure 22 USB timings definition of data signal rise and fall time 90 Figure 23 I2 S slave timing diagram Philips protocol 1 92 Figure 24 I2 S master timing diagram Philips protocol 1 92 Figure 25 ADC accuracy characteristics 96 Figure 26 Typical connection diagram using the ADC 96 Figure 27 Maximum dynamic current consumption on VREF supply pin during ADC conversion 97 Figure 28 12 bit buffered non...

Page 8: ...ily These features make the ultra low power STM32L162xC microcontroller family suitable for a wide range of applications Medical and handheld equipment Application control and user interface PC peripherals gaming GPS and sport equipment Alarm systems wired and wireless sensors video intercom Utility metering This STM32L162xC datasheet should be read in conjunction with the STM32L1xxxx reference ma...

Page 9: ...s time bases Moreover the STM32L162xC devices contain standard and advanced communication interfaces up to two I2Cs three SPIs two I2S three USARTs and an USB The STM32L162xC devices offer up to 23 capacitive sensing channels to simply add a touch sensing functionality to any application They also include a real time clock and a set of backup registers that remain powered in Standby mode Finally t...

Page 10: ...ynchronous mode emulating SPI master I2 S 2 I2 C 2 USART 3 USB 1 GPIOs 51 83 Operation amplifiers 2 12 bit synchronized ADC Number of channels 1 21 1 25 12 bit DAC Number of channels 2 2 LCD COM x SEG 1 4x32 or 8x28 1 4x44 or 8x40 Comparators 2 Capacitive sensing channels 23 23 Max CPU frequency 32 MHz Operating voltage 1 8 V to 3 6 V down to 1 65 V at power down with BOR option 1 65 V to 3 6 V wi...

Page 11: ... highly energy efficient cores with both Harvard architecture and pipelined execution advanced STM8 core for STM8L families and ARM Cortex M3 core for STM32L family In addition specific care for the design architecture has been taken to optimize the mA DMIPS and mA MHz ratios This allows the ultra low power performance to range from 5 up to 33 3 DMIPs 2 2 2 Shared peripherals STM8L15xxx STM32L15xx...

Page 12: ...EXV 3 5 7 26 0 7 N DFNXS 5HJ 57 9 8 5 6 5 06 5 6 DFNXS LQWHUIDFH 9 966 7 0 5 7 0 5 7 0 5 23 03 23 03 63 6 63 6 86 57 86 57 7 0 56 ELWV 7 0 5 7 0 5 7 0 5 RRVWHU 9 9 9 25 3 3 3 6WDQGE LQWHUIDFH 7UDFH RQWUROOHU 70 92 7 5 26 B 1 26 B287 26 B 1 26 B287 7 03 5 9 9 WR 9 KDQQHOV KDQQHOV KDQQHOV KDQQHOV ͺKhdϭ ĂƐ ͺKhdϮ ĂƐ 5 7 76 576 6PDUW DUG DV 5 7 76 576 6PDUW DUG DV 026 0 62 6 166 6 0 6 DV 026 0 62 6 166...

Page 13: ...to the minimum clock 131 kHz execution from SRAM or Flash memory and internal regulator in low power mode to minimize the regulator s operating current In low power run mode the clock frequency and the number of enabled peripherals are both limited Low power sleep mode This mode is achieved by entering Sleep mode with the internal voltage regulator in Low power mode to minimize the regulator s ope...

Page 14: ...ng edge on one of the three WKUP pins RTC alarm Alarm A or Alarm B RTC tamper event RTC timestamp event or RTC Wakeup event occurs Standby mode without RTC Standby mode is used to achieve the lowest power consumption The internal voltage regulator is switched off so that the entire VCORE domain is powered off The PLL MSI RC HSI and LSI RC HSE and LSE crystal oscillators are also switched off After...

Page 15: ... to switch from 4 2 MHz to 32 MHz the user can switch from 4 2 MHz to 16 MHz wait 5 µs then switch from 16 MHz to 32 MHz 2 Should be USB compliant from I O voltage standpoint the minimum VDD is 3 0 V Table 3 Functionalities depending on the operating power supply range continued Functionalities depending on the operating power supply range Operating power supply range DAC and ADC operation USB Dyn...

Page 16: ...Y Y Y EEPROM Y Y Y Y Y Brown out rest BOR Y Y Y Y Y Y Y DMA Y Y Y Y Programmable Voltage Detector PVD Y Y Y Y Y Y Y Power On Reset POR Y Y Y Y Y Y Y Power Down Rest PDR Y Y Y Y Y Y High Speed Internal HSI Y Y High Speed External HSE Y Y Low Speed Internal LSI Y Y Y Y Y Y Low Speed External LSE Y Y Y Y Y Y Multi Speed Internal MSI Y Y Y Y Inter Connect Controller Y Y Y Y RTC Y Y Y Y Y Y Y RTC Tampe...

Page 17: ...Y Y Y Y Comparators Y Y Y Y Y Y 16 bit and 32 bit Timers Y Y Y Y IWDG Y Y Y Y Y Y Y Y WWDG Y Y Y Y Touch sensing Y Y Systic Timer Y Y Y Y GPIOs Y Y Y Y Y Y 3 pins Wakeup time to Run mode 0 µs 0 4 µs 3 µs 46 µs 8 µs 58 µs Consumption VDD 1 8 to 3 6 V Typ Down to 185 µA MHz from Flash Down to 34 5 µA MHz from Flash Down to 8 6 µA Down to 4 4 µA 0 43 µA no RTC VDD 1 8V 0 29 µA no RTC VDD 1 8V 1 15 µA...

Page 18: ...lexible interrupt management features with minimal interrupt latency 3 3 Reset and supply management 3 3 1 Power supply schemes VDD 1 65 to 3 6 V external power supply for I Os and the internal regulator Provided externally through VDD pins VSSA VDDA 1 65 to 3 6 V external analog power supplies for ADC reset blocks RCs and PLL minimum voltage to be applied to VDDA is 1 8 V when the ADC is used VDD...

Page 19: ...ftware with a step around 200 mV An interrupt can be generated when VDD VDDA drops below the VPVD threshold and or when VDD VDDA is higher than the VPVD threshold The interrupt service routine can then generate a warning message and or put the MCU into a safe state The PVD is enabled by software 3 3 3 Voltage regulator The regulator has three operation modes main MR low power LPR and power down MR...

Page 20: ...e MSI frequency can be trimmed by software down to a 0 5 accuracy Auxiliary clock source two ultra low power clock sources that can be used to drive the LCD controller and the real time clock 32 768 kHz low speed external crystal LSE 37 kHz low speed internal RC LSI also used to drive the independent watchdog The LSI clock can be measured using the high speed internal RC oscillator for greater pre...

Page 21: ...EMPO CK PLL PRESCALER 0 0 CK USB 6CO 6CO MUST BE AT Z 4 393 05 072 53 4 4 0 0 USBEN AND NOT DEEPSLEEP TIMER EN AND NOT DEEPSLEEP APB PERIPHEN AND NOT DEEPSLEEP APB PERIPHEN AND NOT DEEPSLEEP NOT SLEEP OR DEEPSLEEP NOT SLEEP OR DEEPSLEEP NOT DEEPSLEEP NOT DEEPSLEEP 3TANDBY SUPPLIED VOLTAGE DOMAIN 3YSTEM CLOCK IF 0 PRESC X ELSE X CK LSE Z 6 2 6 2 6 2 ENABLE 3 2 6 6 2 LEVEL SHIFTERS CK MSI CK LSI ENA...

Page 22: ...e pins can reset backup register and generate an interrupt To prevent false tamper event like ESD event these three tamper inputs can be digitally filtered 3 6 GPIOs general purpose inputs outputs Each of the GPIO pins can be configured by software as output push pull or open drain as input with or without pull up or pull down or as peripheral alternate function Most of the GPIO pins are shared wi...

Page 23: ...atures are connected or boot in RAM is selected Level 2 chip readout protection debug features ARM Cortex M3 JTAG and serial wire and boot in RAM selection disabled JTAG fuse The whole non volatile memory embeds the error correction code ECC feature The user area of the Flash memory can be protected against Dbus read access by PCROP feature see RM0038 for details 3 8 DMA direct memory access The f...

Page 24: ...scan mode In scan mode automatic conversion is performed on a selected group of analog inputs with up to 24 external channels in a group The ADC can be served by the DMA controller An analog watchdog feature allows very precise monitoring of the converted voltage of one some or all scanned channels An interrupt is generated when the converted voltage is outside the programmed thresholds The events...

Page 25: ... is internally connected to the ADC_IN17 input channel It enables accurate monitoring of the VDD value when no external voltage VREF is available for ADC The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area It is accessible in read only mode See Table 16 Embedded internal reference voltage calibration values 3 11 DA...

Page 26: ...combined into a window comparator The internal reference voltage is available externally via a low power low current output buffer driving current capability of 1 µA typical 3 14 System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I O ports The highly flexible routing interface allows the a...

Page 27: ...97 2001 Nov 26 Key scheduler Key derivation for decryption 128 bit data block processed 128 bit key length 213 clock cycles to encrypt decrypt one 128 bit block Electronic codebook ECB cypher block chaining CBC and counter mode CTR supported by hardware AES data flow can be served by 2ch DIN DOUT of the DMA2 controller 3 17 Timers and watchdogs The ultra low power STM32L162xC devices include seven...

Page 28: ...s based on a 16 bit auto reload up down counter They include a 16 bit prescaler TIM10 and TIM11 feature one independent channel whereas TIM9 has two independent channels for input capture output compare PWM or one pulse mode output They can be synchronized with the TIM2 TIM3 TIM4 TIM5 full featured general purpose timers They can also be used as simple time bases and be clocked by the LSE clock so...

Page 29: ...erial peripheral interface SPI Up to three SPIs are able to communicate at up to 16 Mbits s in slave and master modes in full duplex and half duplex communication modes The 3 bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits The hardware CRC generation verification supports basic SD Card MMC modes The SPIs can be served by the DMA controller 3 18 4 In...

Page 30: ...d a fixed generator polynomial Among other applications CRC based techniques are used to verify data transmission or storage integrity In the scope of the EN IEC 60335 1 standard they offer a means of verifying the Flash memory integrity The CRC calculation unit helps compute a signature of the software during runtime to be compared with a reference signature generated at link time and stored at a...

Page 31: ...d with a JTAG fuse 3 20 2 Embedded Trace Macrocell The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L162xC device through a small number of ETM pins to an external hardware trace port analyzer TPA device The TPA is connected to a host computer using USB Ethernet or any ...

Page 32: ...t 1 This figure shows the package top view AI F 0 3 26 B 1 3 26 B287 3 3 83 3 26 B287 3 966 95 95 9 3 3 3 3 8 3 9 966B 9 B 1567 3 3 3 83 3 3 3 3 966B 966B 9 B 3 3 3 3 227 3 9 B 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 966B 9 B 3 3 3 3 3 3 3 3 3 3 966B 9 B 3 3 26 B 1 ...

Page 33: ...This figure shows the package top view 6 633 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 633 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 633 6 6 633 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 50 6 0 7 50 0 3 0 3 54 633 6 0 3 0 3 54 234 0 0 0 0 633 62 62 6 0 7 50 0 0 AI C 1 0 0 0 ...

Page 34: ...81 Rev 10 Figure 5 STM32L162RC LQFP64 pinout 1 This figure shows the package top view 6 0 7 50 0 3 0 3 54 0 3 0 3 54 234 0 0 0 0 633 6 0 7 50 0 0 6 633 0 0 4 0 0 0 0 0 0 0 0 0 0 0 6 633 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 633 6 0 0 0 0 0 0 0 0 0 0 0 633 6 1 0 AI C ...

Page 35: ...a note all I Os are set as floating inputs during and after reset Pin functions Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected enabled through peripheral registers Table 9 STM32L162xC pin definitions Pins Pin name Type 1 I O Level 2 Main function 3 after reset Pin functions UFBGA100 LQFP100 LQFP64 Alternate functions Additional f...

Page 36: ...1 19 12 VSSA S VSSA K1 20 VREF S VREF L1 21 VREF S VREF M1 22 13 VDDA S VDDA L2 23 14 PA0 WKUP1 I O FT PA0 TIM2_CH1_ETR TIM5_CH1 USART2_CTS WKUP1 RTC_TAMP2 ADC_IN0 COMP1_INP M2 24 15 PA1 I O FT PA1 TIM2_CH2 TIM5_CH2 USART2_RTS LCD_SEG0 ADC_IN1 COMP1_INP OPAMP1_VINP K3 25 16 PA2 I O FT PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX LCD_SEG1 ADC_IN2 COMP1_INP OPAMP1_VINM L3 26 17 PA3 I O PA3 TIM2_CH4 TIM5...

Page 37: ... FT PB1 TIM3_CH4 LCD_SEG6 ADC_IN9 COMP1_INP VREF_OUT L6 37 28 PB2 I O FT PB2 BOOT1 BOOT1 ADC_IN0b M7 38 PE7 I O PE7 ADC_IN22 COMP1_INP L7 39 PE8 I O PE8 ADC_IN23 COMP1_INP M8 40 PE9 I O PE9 TIM2_CH1_ETR TIM5_ETR ADC_IN24 COMP1_INP L8 41 PE10 I O PE10 TIM2_CH2 ADC_IN25 COMP1_INP M9 42 PE11 I O FT PE11 TIM2_CH3 L9 43 PE12 I O FT PE12 TIM2_CH4 SPI1_NSS M10 44 PE13 I O FT PE13 SPI1_SCK M11 45 PE14 I O...

Page 38: ..._CTS LCD_SEG31 J10 59 PD12 I O FT PD12 TIM4_CH1 USART3_RTS LCD_SEG32 H12 60 PD13 I O FT PD13 TIM4_CH2 LCD_SEG33 H11 61 PD14 I O FT PD14 TIM4_CH3 LCD_SEG34 H10 62 PD15 I O FT PD15 TIM4_CH4 LCD_SEG35 E12 63 37 PC6 I O FT PC6 TIM3_CH1 I2S2_MCK LCD_SEG24 E11 64 38 PC7 I O FT PC7 TIM3_CH2 I2S3_MCK LCD_SEG25 E10 65 39 PC8 I O FT PC8 TIM3_CH3 LCD_SEG26 D12 66 40 PC9 I O FT PC9 TIM3_CH4 LCD_SEG27 D11 67 4...

Page 39: ...PC12 SPI3_MOSI I2S3_SD USART3_CK LCD_SEG30 LCD_SEG42 LCD_COM6 C9 81 PD0 I O FT PD0 TIM9_CH1 SPI2_NSS I2S2_WS B9 82 PD1 I O FT PD1 SPI2_SCK I2S2_CK C8 83 54 PD2 I O FT PD2 TIM3_ETR LCD_SEG31 LCD_SEG43 LCD_COM7 B8 84 PD3 I O FT PD3 SPI2_MISO USART2_CTS B7 85 PD4 I O FT PD4 SPI2_MOSI I2S2_SD USART2_RTS A6 86 PD5 I O FT PD5 USART2_TX B6 87 PD6 I O FT PD6 USART2_RX A5 88 PD7 I O FT PD7 TIM9_CH2 USART2_...

Page 40: ...The PC14 and PC15 I Os are only configured as OSC32_IN OSC32_OUT when the LSE oscillator is ON by setting the LSEON bit in the RCC_CSR register The LSE oscillator pins OSC32_IN OSC32_OUT can be used as general purpose PH0 PH1 I Os respectively when the LSE oscillator is off after reset the LSE oscillator is off The LSE has priority over the GPIO function For more details refer to Using the OSC32_I...

Page 41: ...IM5_CH3 TIM9_CH1 USART2_TX SEG1 TIMx_IC3 EVENT OUT PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX SEG2 TIMx_IC4 EVENT OUT PA4 SPI1_NSS SPI3_NSS I2S3_WS USART2_CK TIMx_IC1 EVENT OUT PA5 TIM2_CH1_ETR SPI1_SCK TIMx_IC2 EVENT OUT PA6 TIM3_CH1 TIM10_ CH1 SPI1_MISO SEG3 TIMx_IC3 EVENT OUT PA7 TIM3_CH2 TIM11_ CH1 SPI1_MOSI SEG4 TIMx_IC4 EVENT OUT PA8 MCO USART1_CK COM0 TIMx_IC1 EVENT OUT PA9 USART1_TX COM1 TIM...

Page 42: ...T PB10 TIM2_CH3 I2C2_SCL USART3_TX SEG10 EVENT OUT PB11 TIM2_CH4 I2C2_SDA USART3_RX SEG11 EVENT OUT PB12 TIM10_CH1 I2C2_SMBA SPI2_NSS I2S2_WS USART3_CK SEG12 EVENT OUT PB13 TIM9_CH1 SPI2_SCK I2S2_CK USART3_CTS SEG13 EVENT OUT PB14 TIM9_CH2 SPI2_MISO USART3_RTS SEG14 EVENT OUT PB15 TIM11_CH1 SPI2_MOSI I2S2_SD SEG15 EVENT OUT PC0 SEG18 TIMx_IC1 EVENT OUT PC1 SEG19 TIMx_IC2 EVENT OUT PC2 SEG20 TIMx_I...

Page 43: ...41 TIMx_IC4 EVENT OUT PC12 SPI3_MOSI I2S3_SD USART3_CK COM6 SEG30 SEG42 TIMx_IC1 EVENT OUT PC13 WKUP2 TIMx_IC2 EVENT OUT PC14 OSC32_IN TIMx_IC3 EVENT OUT PC15 OSC32_ OUT TIMx_IC4 EVENT OUT PD0 TIM9_CH1 SPI2_NSS I2S2_WS TIMx_IC1 EVENT OUT PD1 SPI2 SCK I2S2_CK TIMx_IC2 EVENT OUT PD2 TIM3_ETR COM7 SEG31 SEG43 TIMx_IC3 EVENT OUT Table 10 Alternate function input output continued Port name Digital alte...

Page 44: ... SEG33 TIMx_IC2 EVENT OUT PD14 TIM4_CH3 SEG34 TIMx_IC3 EVENT OUT PD15 TIM4_CH4 SEG35 TIMx_IC4 EVENT OUT PE0 TIM4_ETR TIM10_CH1 SEG36 TIMx_IC1 EVENT OUT PE1 TIM11_CH1 SEG37 TIMx_IC2 EVENT OUT PE2 TRACECK TIM3_ETR SEG 38 TIMx_IC3 EVENT OUT PE3 TRACED0 TIM3_CH1 SEG 39 TIMx_IC4 EVENT OUT PE4 TRACED1 TIM3_CH2 TIMx_IC1 EVENT OUT PE5 TRACED2 TIM9_CH1 TIMx_IC2 EVENT OUT PE6 WKUP3 TRACED3 TIM9_CH2 TIMx_IC3...

Page 45: ... TIMx_IC1 EVENT OUT PE13 SPI1_SCK TIMx_IC2 EVENT OUT PE14 SPI1_MISO TIMx_IC3 EVENT OUT PE15 SPI1_MOSI TIMx_IC4 EVENT OUT PH0OSC _IN PH1OSC_ OUT PH2 Table 10 Alternate function input output continued Port name Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO11 AFIO14 AFIO15 Alternate function SYSTEM TIM2 TIM3 4 5 TIM9 10 11 I2C1 2 SPI1 2 SPI3 USART1 2 3 LCD CPR...

Page 46: ...2 O RTEX NTERNAL 0ERIPHERALS 3 6 BYTE 53 4 4 4 X X X X X 0ORT 0ORT 0ORT 0ORT 0ORT 0ORT X X X X X X 0 2 LASH MEMORY 3YSTEM MEMORY LIASED TO LASH OR SYSTEM MEMORY DEPENDING ON 4 PINS ATA 02 RESERVED RESERVED RESERVED RESERVED RESERVED ON VOLATILE MEMORY RESERVED PTION BYTE RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X ...

Page 47: ...he mean value plus or minus three times the standard deviation mean 3σ 6 1 2 Typical values Unless otherwise specified typical data are based on TA 25 C VDD 3 6 V for the 1 65 V VDD 3 6 V voltage range They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperatu...

Page 48: ...ev 10 6 1 6 Power supply scheme Figure 9 Power supply scheme 06 9 QDORJ 26 3 203 9 3 2V 287 1 HUQHO ORJLF 38 LJLWDO 0HPRULHV 6WDQGE SRZHU FLUFXLWU 6 57 DNH XS ORJLF 57 EDFNXS UHJLVWHUV 1 î Q î 5HJXODWRU 966 9 95 95 966 HYHO VKLIWHU 2 RJLF 9 Q 95 Q 9 1 QXPEHU RI 9 966 SDLUV ...

Page 49: ...itch is open 2 Option 2 LCD power supply is provided by the internal step up converter VSEL switch is closed an external capacitance is needed for correct behavior of this converter 6 1 8 Current consumption measurement Figure 11 Current consumption measurement scheme 06 9 9 1 1 Q 6WHS XS RQYHUWHU 966 1 9 Q 9 9 UDLO 9 UDLO 9 UDLO 9 3 RU 3 3 3 RU 3 7 UDLO 96 UDLO UDLO 2SWLRQ 2SWLRQ 1 Q 1 966 1 9 96...

Page 50: ... maximum must always be respected Refer to Table 12 for maximum allowed injected current values 3 Include VREF pin Table 12 Current characteristics Symbol Ratings Max Unit IVDD Σ Total current into sum of all VDD_x power lines source 1 100 mA IVSS Σ 2 Total current out of sum of all VSS_x ground lines sink 1 100 IVDD PIN Maximum current into each VDD_x power pin source 1 70 IVSS PIN Maximum curren...

Page 51: ... Symbol Ratings Value Unit TSTG Storage temperature range 65 to 150 C TJ Maximum junction temperature 150 C Table 14 General operating conditions Symbol Parameter Conditions Min Max Unit fHCLK Internal AHB clock frequency 0 32 MHz fPCLK1 Internal APB1 clock frequency 0 32 fPCLK2 Internal APB2 clock frequency 0 32 VDD Standard operating voltage BOR detector disabled 1 65 3 6 V BOR detector enabled ...

Page 52: ... long as TJ does not exceed TJ max see Table 70 Thermal characteristics on page 114 5 In low power dissipation state TA can be extended to 40 C to 105 C temperature range as long as TJ does not exceed TJ max see Table 70 Thermal characteristics on page 114 Table 14 General operating conditions continued Symbol Parameter Conditions Min Max Unit Table 15 Embedded reset and power control block charac...

Page 53: ...2 38 VPVD3 PVD threshold 3 Falling edge 2 39 2 44 2 48 Rising edge 2 47 2 54 2 58 VPVD4 PVD threshold 4 Falling edge 2 57 2 64 2 69 Rising edge 2 68 2 74 2 79 VPVD5 PVD threshold 5 Falling edge 2 77 2 83 2 88 Rising edge 2 87 2 94 2 99 VPVD6 PVD threshold 6 Falling edge 2 97 3 05 3 09 Rising edge 3 08 3 15 3 20 Vhyst Hysteresis voltage BOR0 threshold 40 mV All BOR and PVD thresholds excepting BOR0...

Page 54: ... Including uncertainties due to ADC and VDDA VREF values 5 mV TCoeff 3 Temperature coefficient 40 C TJ 110 C 25 100 ppm C ACoeff 3 Long term stability 1000 hours T 25 C 1000 ppm VDDCoeff 3 Voltage coefficient 3 0 V VDDA 3 6 V 2000 ppm V TS_vrefint 3 ADC sampling time when reading the internal reference voltage 4 µs TADC_BUF 3 4 Startup time of reference voltage buffer for ADC 10 µs IBUF_ADC 3 Cons...

Page 55: ...ply voltage conditions summarized in Table 14 General operating conditions unless otherwise specified The MCU is placed under the following conditions All I O pins are configured in analog input mode All peripherals are disabled except when explicitly mentioned The Flash memory access time 64 bit access and prefetch is adjusted depending on fHCLK frequency and voltage range to provide the best CPU...

Page 56: ... 1 0 11 1 MHz 215 400 µA 2 MHz 400 600 4 MHz 725 960 Range 2 VCORE 1 5 V VOS 1 0 10 4 MHz 0 915 1 1 mA 8 MHz 1 75 2 1 16 MHz 3 4 3 9 Range 1 VCORE 1 8 V VOS 1 0 01 8 MHz 2 1 2 8 16 MHz 4 2 4 9 32 MHz 8 25 9 4 HSI clock source 16 MHz Range 2 VCORE 1 5 V VOS 1 0 10 16 MHz 3 5 4 Range 1 VCORE 1 8 V VOS 1 0 01 32 MHz 8 2 9 6 MSI clock 65 kHz Range 3 VCORE 1 2 V VOS 1 0 11 65 kHz 40 5 110 µA MSI clock ...

Page 57: ...A 2 MHz 345 410 4 MHz 645 880 3 Range 2 VCORE 1 5 V VOS 1 0 10 4 MHz 0 755 1 4 mA 8 MHz 1 5 2 1 16 MHz 3 3 5 Range 1 VCORE 1 8 V VOS 1 0 01 8 MHz 1 8 2 8 16 MHz 3 6 4 1 32 MHz 7 15 8 3 HSI clock source 16 MHz Range 2 VCORE 1 5 V VOS 1 0 10 16 MHz 2 95 3 5 Range 1 VCORE 1 8 V VOS 1 0 01 32 MHz 7 15 8 4 MSI clock 65 kHz Range 3 VCORE 1 2 V VOS 1 0 11 65 kHz 38 5 85 µA MSI clock 524 kHz 524 kHz 110 1...

Page 58: ...kHz Range 3 VCORE 1 2 V VOS 1 0 11 65 kHz 19 60 MSI clock 524 kHz 524 kHz 33 99 MSI clock 4 2 MHz 4 2 MHz 145 210 Supply current in Sleep mode Flash ON fHSE fHCLK up to 16 MHz included fHSE fHCLK 2 above 16 MHz PLL ON 2 Range 3 VCORE 1 2 V VOS 1 0 11 1 MHz 60 5 130 2 MHz 89 5 190 4 MHz 150 320 Range 2 VCORE 1 5 V VOS 1 0 10 4 MHz 180 320 8 MHz 320 460 16 MHz 605 840 Range 1 VCORE 1 8 V VOS 1 0 01 ...

Page 59: ...14 16 TA 85 C 24 29 TA 105 C 40 51 MSI clock 131 kHz fHCLK 131 kHz TA 40 C to 25 C 26 29 TA 55 C 28 31 TA 85 C 36 42 TA 105 C 52 64 All peripherals OFF code executed from Flash VDD from 1 65 V to 3 6 V MSI clock 65 kHz fHCLK 32 kHz TA 40 C to 25 C 20 24 TA 85 C 32 37 TA 105 C 49 61 MSI clock 65 kHz fHCLK 65 kHz TA 40 C to 25 C 26 30 TA 85 C 38 44 TA 105 C 55 67 MSI clock 131 kHz fHCLK 131 kHz TA 4...

Page 60: ...65 kHz Flash ON TA 40 C to 25 C 15 17 TA 85 C 20 23 TA 105 C 28 33 MSI clock 131 kHz fHCLK 131 kHz Flash ON TA 40 C to 25 C 17 19 TA 55 C 18 21 TA 85 C 22 25 TA 105 C 30 35 TIM9 and USART1 enabled Flash ON VDD from 1 65 V to 3 6 V MSI clock 65 kHz fHCLK 32 kHz TA 40 C to 25 C 14 16 TA 85 C 19 22 TA 105 C 27 32 MSI clock 65 kHz fHCLK 65 kHz TA 40 C to 25 C 15 17 TA 85 C 20 23 TA 105 C 28 33 MSI clo...

Page 61: ...0 TA 105 C 6 35 23 LCD ON static duty 2 TA 40 C to 25 C 1 55 6 TA 55 C 2 15 7 TA 85 C 3 55 12 TA 105 C 6 3 27 LCD ON 1 8 duty 3 TA 40 C to 25 C 3 9 10 TA 55 C 4 65 11 TA 85 C 6 25 16 TA 105 C 9 1 44 RTC clocked by LSE external quartz 32 768kHz regulator in LP mode HSI and HSE OFF no independent watchdog 4 LCD OFF TA 40 C to 25 C 1 5 TA 55 C 2 15 TA 85 C 3 7 TA 105 C 6 75 LCD ON static duty 2 TA 40...

Page 62: ...acterization results unless otherwise specified 2 LCD enabled with external VLCD static duty division ratio 256 all pixels active no LCD connected 3 LCD enabled with external VLCD 1 8 duty 1 3 bias division ratio 64 all pixels active no LCD connected 4 Based on characterization done with a 32 768 kHz crystal MC306 G 06Q 32 768 manufacturer JFVNY with two 6 8 pF loading capacitors 5 Guaranteed by t...

Page 63: ...bled RTC clocked by LSI no independent watchdog TA 40 C to 25 C VDD 1 8 V 0 905 µA TA 40 C to 25 C 1 15 1 9 TA 55 C 1 5 2 2 TA 85 C 1 750 4 TA 105 C 2 1 8 3 2 RTC clocked by LSE external quartz no independent watchdog 3 TA 40 C to 25 C VDD 1 8 V 0 98 TA 40 C to 25 C 1 3 TA 55 C 1 7 TA 85 C 2 05 TA 105 C 2 45 IDD Standby Supply current in Standby mode RTC disabled Independent watchdog and LSI enabl...

Page 64: ...E 1 2 V VOS 1 0 11 Low power sleep and run APB1 TIM2 11 2 8 9 7 0 8 9 µA MHz fHCLK TIM3 11 2 9 0 7 1 9 0 TIM4 12 9 10 4 8 2 10 4 TIM5 14 4 11 5 9 0 11 5 TIM6 4 0 3 1 2 4 3 1 TIM7 3 8 3 0 2 3 3 0 LCD 5 8 4 6 3 6 4 6 WWDG 2 9 2 3 1 8 2 3 SPI2 6 5 5 2 4 1 5 2 SPI3 5 9 4 6 3 6 4 6 USART2 8 8 7 0 5 5 7 0 USART3 8 4 6 8 5 3 6 8 I2C1 7 3 5 8 4 6 5 8 I2C2 7 9 6 3 5 0 6 3 USB 13 3 10 6 8 3 10 6 PWR 2 8 2 2...

Page 65: ... µA IDD LCD 3 1 IDD ADC 4 1450 IDD DAC 5 340 IDD COMP1 0 16 IDD COMP2 Slow mode 2 Fast mode 5 IDD PVD BOR 6 2 6 IDD IWDG 0 25 1 Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled in the following conditions fHCLK 32 MHz range 1 fHCLK 16 MHz range 2 fHCLK 4 MHz range 3 fHCLK 64kHz Low power run sleep fAPB1 fHCLK fAPB2 fHCLK default prescaler ...

Page 66: ...tion not included 5 Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of VDD 2 DAC is in buffered mode output is left floating 6 Including supply current of internal reference voltage Table 26 Low power mode wakeup timings Symbol Parameter Conditions Typ Max 1 Unit tWUSLEEP Wakeup from Sleep mode fHCLK 32 MHz 0 4 µs tWUSLEEP_LP Wakeup fro...

Page 67: ...ed external clock source AC timing diagram 1 Guaranteed by characterization unless otherwise specified Table 27 High speed external user clock characteristics 1 1 Guaranteed by design Symbol Parameter Conditions Min Typ Max Unit fHSE_ext User external clock source frequency CSS is on or PLL is used 1 8 32 MHz CSS is off PLL not used 0 8 32 MHz VHSEH OSC_IN input pin high level voltage 0 7VDD VDD V...

Page 68: ...th typical external components specified in Table 29 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details on the resonator characteristics frequency package accuracy Table 28 Low speed external user cloc...

Page 69: ...r 200 kΩ C Recommended load capacitance versus equivalent serial resistance of the crystal RS 3 RS 30 Ω 20 pF IHSE HSE driving current VDD 3 3 V VIN VSS with 30 pF load 3 mA IDD HSE HSE oscillator power consumption C 20 pF fOSC 16 MHz 2 5 startup 0 7 stabilized mA C 10 pF fOSC 16 MHz 2 5 startup 0 46 stabilized gm Oscillator transconductance Startup 3 5 mA V tSU HSE 4 Startup time VDD is stabilize...

Page 70: ...accuracy Table 30 LSE oscillator characteristics fLSE 32 768 kHz 1 1 Guaranteed by characterization results Symbol Parameter Conditions Min Typ Max Unit fLSE Low speed external oscillator frequency 32 768 kHz RF Feedback resistor 1 2 MΩ C 2 2 Refer to the note and caution paragraphs below the table and to the application note AN2867 Oscillator design guide for ST microcontrollers Recommended load ...

Page 71: ...ally it is between 2 pF and 7 pF Caution To avoid exceeding the maximum value of CL1 and CL2 15 pF it is strongly recommended to use a resonator with a load capacitance CL 7 pF Never use a resonator with a load capacitance of 12 5 pF Example if the user chooses a resonator with a load capacitance of CL 6 pF and Cstray 2 pF then CL1 CL2 8 pF Figure 15 Typical application with a 32 768 kHz crystal 4...

Page 72: ...ode is a multiple of 16 1 5 ACCHSI 2 2 Guaranteed by characterization results Accuracy of the factory calibrated HSI oscillator VDDA 3 0 V TA 25 C 1 3 3 Guaranteed by test in production 1 3 VDDA 3 0 V TA 0 to 55 C 1 5 1 5 VDDA 3 0 V TA 10 to 70 C 2 2 VDDA 3 0 V TA 10 to 85 C 2 5 2 VDDA 3 0 V TA 10 to 105 C 4 2 VDDA 1 65 V to 3 6 V TA 40 to 105 C 4 3 tSU HSI 2 HSI oscillator startup time 3 7 6 µs I...

Page 73: ... MSI range 6 4 2 ACCMSI Frequency error after factory calibration 0 5 DTEMP MSI 1 MSI oscillator frequency drift 0 C TA 105 C 3 DVOLT MSI 1 MSI oscillator frequency drift 1 65 V VDD 3 6 V TA 25 C 2 5 V IDD MSI 2 MSI oscillator power consumption MSI range 0 0 75 µA MSI range 1 1 MSI range 2 1 5 MSI range 3 2 5 MSI range 4 4 5 MSI range 5 8 MSI range 6 15 tSU MSI MSI oscillator startup time MSI rang...

Page 74: ...2 5 MSI range 5 2 MSI range 6 Voltage range 1 and 2 2 MSI range 3 Voltage range 3 3 fOVER MSI MSI oscillator frequency overshoot Any range to range 5 4 MHz Any range to range 6 6 1 This is a deviation for an individual part once the initial frequency has been measured 2 Guaranteed by characterization results Table 33 MSI oscillator characteristics continued Symbol Parameter Condition Typ Max Unit ...

Page 75: ...of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT 2 24 MHz PLL input clock duty cycle 45 55 fPLL_OUT PLL output clock 2 32 MHz tLOCK PLL lock time PLL input 16 MHz PLL VCO 96 MHz 115 160 µs Jitter Cycle to cycle jitter 600 ps IDDA PLL Current consumption on VDDA 220 450 µA IDD PLL Current consumption on VDD 120 150 Table ...

Page 76: ...mum current peak during the whole programming erase operation 1 5 2 5 mA Table 37 Flash memory and data EEPROM endurance and retention Symbol Parameter Conditions Value Unit Min 1 1 Guaranteed by characterization results Typ Max NCYC 2 Cycling erase write Program memory TA 40 C to 105 C 10 kcycles Cycling erase write EEPROM data memory 300 tRET 2 2 Characterization is done according to JEDEC JESD2...

Page 77: ...racterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for h...

Page 78: ...lectrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pins This test conforms to the JESD22 A114 ANSI ESD STM5 3 1 standard Table 39 EMI characteristics Symbol Parameter Conditions Monitor...

Page 79: ...ed on the device the device is stressed by injecting current into the I O pins programmed in floating input mode While current is injected into the I O pin one at a time the device is checked for functional failures The failure is indicated by an out of range parameter ADC error above a certain limit higher than 5 LSB TUE out of conventional limits of induced leakage current on adjacent pins out o...

Page 80: ...gger voltage hysteresis 2 TC and FT I O 10 VDD 3 BOOT0 0 01 Ilkg Input leakage current 4 VSS VIN VDD I Os with LCD 50 nA VSS VIN VDD I Os with analog switches 50 VSS VIN VDD I Os with analog switches and LCD 50 VSS VIN VDD I Os with USB 250 VSS VIN VDD TC and FT I Os 50 FT I O VDD VIN 5V 10 µA RPU Weak pull up equivalent resistor 5 1 VIN VSS 30 45 60 kΩ RPD Weak pull down equivalent resistor 5 VIN...

Page 81: ... derived from tests performed under the conditions summarized in Table 14 All I Os are CMOS and TTL compliant Table 44 Output voltage characteristics Symbol Parameter Conditions Min Max Unit VOL 1 2 1 The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO I O ports and control pins must not exceed IVSS 2 Guaranteed by test in pro...

Page 82: ...VDD 2 7 V to 3 6 V 2 MHz CL 50 pF VDD 1 65 V to 2 7 V 1 tf IO out tr IO out Output rise and fall time CL 50 pF VDD 2 7 V to 3 6 V 125 ns CL 50 pF VDD 1 65 V to 2 7 V 250 10 Fmax IO out Maximum frequency 3 CL 50 pF VDD 2 7 V to 3 6 V 10 MHz CL 50 pF VDD 1 65 V to 2 7 V 2 tf IO out tr IO out Output rise and fall time CL 50 pF VDD 2 7 V to 3 6 V 25 ns CL 50 pF VDD 1 65 V to 2 7 V 125 11 Fmax IO out M...

Page 83: ... OUT Table 46 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL NRST 1 NRST input low level voltage 0 3 VDD V VIH NRST 1 NRST input high level voltage 0 39VDD 0 59 VOL NRST 1 NRST output low level voltage IOL 2 mA 2 7 V VDD 3 6 V 0 4 IOL 1 5 mA 1 65 V VDD 2 7 V Vhys NRST 1 NRST Schmitt trigger voltage hysteresis 10 VDD 2 mV RPU Weak pull up equivalent resistor 3 VIN VSS 30 ...

Page 84: ...on the input output ction characteristics output compare input capture external clock PWM output DL E 670 538 1567 9 LOWHU QWHUQDO UHVHW WHUQDO UHVHW FLUFXLW Table 47 TIMx 1 characteristics 1 TIMx is used as a general term to refer to the TIM2 TIM3 and TIM4 timers Symbol Parameter Conditions Min Max Unit tres TIM Timer resolution time 1 tTIMxCLK fTIMxCLK 32 MHz 31 25 ns fEXT Timer external clock f...

Page 85: ... I C frequencies It must be at least 4 MHz to achieve fast mode I C frequencies It must be a multiple of 10 MHz to reach the 400 kHz maximum I C fast mode clock Unit Min Max Min Max tw SCLL SCL clock low time 4 7 1 3 µs tw SCLH SCL clock high time 4 0 0 6 tsu SDA SDA setup time 250 100 ns th SDA SDA data hold time 3450 3 900 3 3 The maximum Data hold time has only to be met if the interface does n...

Page 86: ...DD_I2C 3 3 V 1 2 1 RP External pull up resistance fSCL I2C speed 2 For speeds around 200 kHz the tolerance on the achieved speed is of 5 For other speed ranges the tolerance on the achieved speed is 2 These variations depend on the accuracy of the external components used to design the application fSCL kHz I2C_CCR value RP 4 7 kΩ 400 0x801B 300 0x8024 200 0x8035 100 0x00A0 50 0x0140 20 0x0320 Ăŝϭϳ...

Page 87: ...mode 30 70 tsu NSS NSS setup time Slave mode 4tHCLK ns th NSS NSS hold time Slave mode 2tHCLK tw SCKH 2 tw SCKL 2 SCK high and low time Master mode tSCK 2 5 tSCK 2 3 tsu MI 2 Data input setup time Master mode 5 tsu SI 2 Slave mode 6 th MI 2 Data input hold time Master mode 5 th SI 2 Slave mode 5 ta SO 4 Data output access time Slave mode 0 3tHCLK tv SO 2 Data output valid time Slave mode 33 tv MO ...

Page 88: ...Measurement points are done at CMOS levels 0 3VDD and 0 7VDD DL F 6 QSXW 166 LQSXW W68 166 WF 6 WK 166 3 32 3 32 WZ 6 WZ 6 W9 62 WK 62 WU 6 WI 6 WGLV 62 WD 62 0 62 287387 026 1387 06 287 7 287 6 287 WVX 6 WK 6 06 1 7 1 6 1 DL E 166 LQSXW W68 166 WF 6 WK 166 6 LQSXW 3 32 3 32 WZ 6 WZ 6 WD 62 WY 62 WK 62 WU 6 WI 6 WGLV 62 0 62 287387 026 1387 WVX 6 WK 6 06 287 06 1 7 287 6 287 6 1 7 1 ...

Page 89: ...re 21 SPI timing diagram master mode 1 1 Measurement points are done at CMOS levels 0 3VDD and 0 7VDD DL F 6 2XWSXW 3 026 287387 0 62 1387 3 6 287 6 1 32 32 7 287 166 LQSXW WF 6 WZ 6 WZ 6 WU 6 WI 6 WK 0 LJK 6 2XWSXW 3 3 32 32 WVX 0 WY 02 WK 02 06 1 7 1 06 287 ...

Page 90: ...VDD USB operating voltage 3 0 3 6 V VDI 2 2 Guaranteed by characterization results Differential input sensitivity I USB_DP USB_DM 0 2 V VCM 2 Differential common mode range Includes VDI range 0 8 2 5 VSE 2 Single ended receiver threshold 1 3 2 0 Output levels VOL 3 3 Guaranteed by test in production Static output level low RL of 1 5 kΩ to 3 6 V 4 4 RL is the load connected on the USB drivers 0 3 V...

Page 91: ...CK I2S clock frequency Master data 32 bits 64xFs MHz Slave data 32 bits 64xFs DCK I2S clock frequency duty cycle Slave receiver 48KHz 30 70 tr CK I2S clock rise time Capacitive load CL 30pF 8 ns tf CK I2S clock fall time 8 tv WS WS valid time Master mode 4 24 th WS WS hold time Master mode 0 tsu WS WS setup time Slave mode 15 th WS WS hold time Slave mode 0 tsu SD_MR Data input setup time Master r...

Page 92: ...eceive is sent before the first byte Figure 24 I2 S master timing diagram Philips protocol 1 1 Guaranteed by characterization results 2 LSB transmit receive of the previously transmitted byte No LSB transmit receive is sent before the first byte QSXW 32 32 WF 6 LQSXW 6 WUDQVPLW 6 UHFHLYH WZ WZ WVX 6 WY 6 B67 WK 6 B67 WK 6 WVX 6 B65 WK 6 B65 06 UHFHLYH LWQ UHFHLYH 6 UHFHLYH 06 WUDQVPLW LWQ WUDQVPLW...

Page 93: ... 3 4 Table 56 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 1 8 3 6 V VREF Positive reference voltage 1 8 1 VDDA VREF Negative reference voltage VSSA IVDDA Current on the VDDA input pin 1000 1450 µA IVREF 2 Current on the VREF input pin Peak 400 700 Average 450 VAIN Conversion voltage range 3 0 4 VREF V fS 12 bit sampling rate Direct channels 1 Msps Multiplexed...

Page 94: ...gger conversion latency fADC 16 MHz 156 219 ns 2 5 3 5 1 fADC tSTAB Power up time 3 5 µs 1 The Vref input can be grounded if neither the ADC nor the DAC are used this allows to shut down an external voltage reference 2 The current consumption through VREF is composed of two parameters one constant max 300 µA one variable max 400 µA only during sampling time 2 first conversion pulses So peak consum...

Page 95: ...c distortion 70 65 ET Total unadjusted error 2 4 V VDDA 3 6 V 1 8 V VREF 2 4 V fADC 4 MHz RAIN 50 Ω TA 40 to 105 C 4 6 5 LSB EO Offset error 2 4 EG Gain error 4 6 ED Differential linearity error 1 2 EL Integral linearity error 1 5 3 ET Total unadjusted error 1 8 V VDDA 2 4 V 1 8 V VREF 2 4 V fADC 4 MHz RAIN 50 Ω TA 40 to 105 C 2 3 LSB EO Offset error 1 1 5 EG Gain error 1 5 2 ED Differential linea...

Page 96: ...uracy To remedy this fADC should be reduced DPSOH RI DQ DFWX DO WUDQVIHU FXUYH 7KH LGHDO WUDQVIHU FXUYH QG SRLQW FRUUHODWLRQ OLQH DL H 7 7RWDO XQDGMXVWHG UURU PD LPXP GHYLDWLRQ EHWZHHQ WKH DFWXDO DQG WKH LGHDO WUDQVIHU FXUYHV 2 2IIVHW UURU GHYLDWLRQ EHWZHHQ WKH ILUVW DFWXDO WUDQVLWLRQ DQG WKH ODVW DFWXDO RQH DLQ UURU GHYLDWLRQ EHWZHHQ WKH ODVW LGHDO WUDQVLWLRQ DQG WKH ODVW DFWXDO RQH LIIHUHQWLDO L...

Page 97: ... Conversion 12 cycles Iref 300µA 700µA MS36686V1 Table 58 Maximum source impedance RAIN max 1 Ts µs RAIN max kΩ Ts cycles fADC 16 MHz 2 Multiplexed channels Direct channels 2 4 V VDDA 3 6 V 1 8 V VDDA 2 4 V 2 4 V VDDA 3 6 V 1 8 V VDDA 2 4 V 0 25 Not allowed Not allowed 0 7 Not allowed 4 0 5625 0 8 Not allowed 2 0 1 0 9 1 2 0 0 8 4 0 3 0 16 1 5 3 0 1 8 6 0 4 5 24 3 6 8 4 0 15 0 10 0 48 6 15 0 10 0 ...

Page 98: ... 3 3 V No load middle code 0x800 210 320 No load worst code 0xF1C 320 520 RL 2 Resistive load DAC output buffer ON 5 kΩ CL 2 Capacitive load 50 pF RO Output impedance DAC output buffer OFF 12 16 20 kΩ VDAC_OUT Voltage on DAC_OUT output DAC output buffer ON 0 2 VDDA 0 2 V DAC output buffer OFF 0 5 VREF 1LSB mV DNL 1 Differential non linearity 3 CL 50 pF RL 5 kΩ DAC output buffer ON 1 5 3 LSB No RL ...

Page 99: ...kΩ DAC output buffer ON 12 30 LSB No RL CL 50 pF DAC output buffer OFF 8 12 tSETTLING Settling time full scale for a 12 bit code transition between the lowest and the highest input codes till DAC_OUT reaches final value 1LSB CL 50 pF RL 5 kΩ 7 12 µs Update rate Max frequency for a correct DAC_OUT change 95 of final value with 1 LSB variation in the input code CL 50 pF RL 5 kΩ 1 Msps tWAKEUP Wakeup...

Page 100: ...lope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF and from code giving 0 2 V and VDDA 0 2 V when buffer is ON 8 In buffered mode the output can overshoot above the final value for low input code starting from min value 5 XIIHUHG 1RQ EXIIHUHG B287 XIIHU ELW GLJLWDO WR DQDORJ FRQYHUWHU AI 6 Table 60 Operational amplifier characteristics Symbol Par...

Page 101: ...CL Capacitive load 50 pF VOHSAT High saturation voltage Normal mode ILOAD max or RL min VDD 100 mV Low power mode VDD 50 VOLSAT Low saturation voltage Normal mode 100 Low power mode 50 ϕm Phase margin 60 GM Gain margin 12 dB tOFFTRIM Offset trim time during calibration minimum time needed between two steps to have 1 mV accuracy 1 ms tWAKEUP Wakeup time Normal mode CL 50 pf RL 4 kΩ 10 µs Low power ...

Page 102: ...1 Average slope 1 48 1 61 1 75 mV C V110 Voltage at 110 C 5 C 2 2 Measured at VDD 3 V 10 mV V110 ADC conversion result is stored in the TS_CAL2 byte 612 626 8 641 5 mV IDDA TEMP 3 Current consumption 3 4 6 µA tSTART 3 3 Guaranteed by design Startup time 10 µs TS_temp 3 ADC sampling time when reading the temperature 4 Table 63 Comparator 1 characteristics Symbol Parameter Conditions Min 1 Typ Max 1...

Page 103: ...omparator startup time Fast mode 15 20 µs Slow mode 20 25 td slow Propagation delay 2 in slow mode 2 The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input the non inverting input set to the reference 1 65 V VDDA 2 7 V 1 8 3 5 2 7 V VDDA 3 6 V 2 5 6 td fast Propagation delay 2 in fast mode 1 65 V VDDA 2 7 V 0 8 2 2 7 V VDDA 3 6 V 1 2 4 Voffset Comparator offse...

Page 104: ... LCD internal reference voltage 6 3 4 VLCD7 LCD internal reference voltage 7 3 55 Cext VLCD external capacitance 0 1 2 µF ILCD 1 1 LCD enabled with 3 V internal step up active 1 8 duty 1 4 bias division ratio 64 all pixels active no LCD connected Supply current at VDD 2 2 V 3 3 µA Supply current at VDD 3 0 V 3 1 RHtot 2 2 Guaranteed by design Low drive resistive network overall value 5 28 6 6 7 92...

Page 105: ...ct status are available at www st com ECOPACK is an ST trademark 7 1 LQFP100 14 x 14 mm 100 pin low profile quad flat package information Figure 29 LQFP100 14 x 14 mm 100 pin low profile quad flat package outline 1 Drawing is not to scale Table 66 LQPF100 14 x 14 mm 100 pin low profile quad flat package mechanical data Symbol millimeters inches 1 Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 1...

Page 106: ... D1 13 800 14 000 14 200 0 5433 0 5512 0 5591 D3 12 000 0 4724 E 15 800 16 000 16 200 0 6220 0 6299 0 6378 E1 13 800 14 000 14 200 0 5433 0 5512 0 5591 E3 12 000 0 4724 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits Table 66 LQPF100 14 x 14 mm 100 pin low pro...

Page 107: ... or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qual...

Page 108: ... not to scale Table 67 LQFP64 10 x 10 mm 64 pin low profile quad flat package mechanical data Symbol millimeters inches 1 Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 c 0 090 0 200 0 0035 0 0079 D 12 000 0 4724 D1 10 000 0 3937 D3 7 500 0 2953 E 12 000 0 4724 E1 10 000 0 3937 B0 B9 6 7 1 3 1 F...

Page 109: ...e in millimeters E3 7 500 0 2953 e 0 500 0 0197 K 0 3 5 7 0 3 5 7 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits Table 67 LQFP64 10 x 10 mm 64 pin low profile quad flat package mechanical data continued Symbol millimeters inches 1 Min Typ Max Min Typ Max AI C ...

Page 110: ...as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to r...

Page 111: ... 0 0181 0 0209 0 0236 A1 0 050 0 080 0 110 0 0020 0 0031 0 0043 A2 0 400 0 450 0 500 0 0157 0 0177 0 0197 A3 0 080 0 130 0 180 0 0031 0 0051 0 0071 A4 0 270 0 320 0 370 0 0106 0 0126 0 0146 b 0 200 0 250 0 300 0 0079 0 0098 0 0118 D 6 950 7 000 7 050 0 2736 0 2756 0 2776 D1 5 450 5 500 5 550 0 2146 0 2165 0 2185 E 6 950 7 000 7 050 0 2736 0 2756 0 2776 E1 5 450 5 500 5 550 0 2146 0 2165 0 2185 e 0...

Page 112: ...nded to 4 decimal digits Table 69 UFBGA100 7 x 7 mm 0 50 mm pitch recommended PCB design rules Dimension Recommended values Pitch 0 5 Dpad 0 280 mm Dsm 0 370 mm typ depends on the soldermask registration tolerance Stencil opening 0 280 mm Stencil thickness Between 0 100 mm and 0 125 mm Table 68 UFBGA100 7 x 7 mm 0 5 mm pitch package mechanical data continued Symbol millimeters inches 1 Min Typ Max...

Page 113: ...panied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification...

Page 114: ...f IDD and VDD expressed in Watts This is the maximum chip internal power PI O max represents the maximum power dissipation on output pins where PI O max Σ VOL IOL Σ VDD VOH IOH taking into account the actual VOL IOL and VOH IOH of the I Os at low and high level in the application Figure 38 Thermal resistance suffix 6 Table 70 Thermal characteristics Symbol Parameter Value Unit ΘJA Thermal resistan...

Page 115: ... Figure 39 Thermal resistance suffix 7 7 4 1 Reference document JESD51 2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection Still Air Available from www jedec org 06Y 9 RUELGGHQ DUHD 7 7 PD 4 3 PP 4 3 PP 8 PP 3 P 7HPSHUDWXUH ...

Page 116: ...32 L 162 V C T 6 D TR Device family STM32 ARM based 32 bit microcontroller Product type L Low power Device subfamily 162 Devices with LCD Pin count R 64 pins V 100 pins Flash memory size C 256 Kbytes of Flash memory Package T LQFP H BGA Temperature range 6 Industrial temperature range 40 to 85 C 7 Industrial temperature range 40 to 105 C Options No character VDD range 1 8 to 3 6 V and BOR enabled ...

Page 117: ...NADV for AFIO12 in Table 10 Alternate function input output Removed caution note below Figure 8 Power supply scheme Added Note 2 in Table 15 Embedded reset and power control block characteristics Updated Table 22 Typical and maximum current consumptions in Stop mode and added Note 6 Updated Table 23 Typical and maximum current consumptions in Standby mode Updated tWUSTOP in Table Updated Table 25 ...

Page 118: ...e Section 7 Package characteristics Updated Figure 25 Typical connection diagram using the ADC and definition of symbol RAIN in Table 55 ADC characteristics Removed first sentence in Section I2C interface characteristics 19 Jul 2013 4 Removed STM32L162QC and STM32L162ZC part numbers including all associated features Updated dThreshold dt conditions in Table 62 Comparator 2 characteristics Updated ...

Page 119: ...al operating conditions footnote and added row Updated Section 6 3 4 Supply current characteristics Updated Table 18 Current consumption in Run mode code with data processing running from Flash Updated Table 21 Current consumption in Run mode code with data processing running from RAM Created Section 6 3 5 Wakeup time from low power mode Updated Chapter 6 3 6 External clock source characteristics ...

Page 120: ...r device continuum Updated Table 3 Functionalities depending on the operating power supply range Updated Table 5 Functionalities depending on the working mode from Run active down to standby Added row VREF VDDA and updated IIO in Table 11 Voltage characteristics Modified IIO maximum values in Table 12 Current characteristics Added input voltage in Table 14 General operating conditions Moved Table ...

Page 121: ... grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Updated the conditions in Table 26 Low power mode wakeup timings Removed ambiguity of ambient temperature in the electrical characteristics description 13 Oct 2014 7 Updated Section 3 18 Communication int...

Page 122: ... Mar 2016 10 Updated cover page putting eight SPIs in the peripheral communication interface list Updated Table 2 Ultra low power STM32L162xC device features and peripheral counts SPI and I2S lines Updated Table 40 ESD absolute maximum ratings CDM class Updated all the notes removing not tested in production Updated Table 11 Voltage characteristics adding note about VREF pin Updated Table 5 Functi...

Page 123: ...gement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for su...

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