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STM32L162VC, STM32L162RC
104
I2S characteristics
Note:
Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), f
MCK
, f
CK
and D
CK
values. These values reflect only the digital peripheral
behavior, source clock precision might slightly change them. DCK depends mainly on the
t
rfm
Rise/ fall time matching
t
r
/t
f
90
110
%
V
CRS
Output signal crossover voltage
1.3
2.0
V
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
Table 54. I2S characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
f
MCK
I2S Main Clock Output
256 x 8K 256xFs
(1)
1. The maximum for 256xFs is 8 MHz
MHz
f
CK
I2S clock frequency
Master data: 32 bits
-
64xFs
MHz
Slave data: 32 bits
-
64xFs
D
CK
I2S clock frequency duty cycle Slave receiver, 48KHz
30
70
%
t
r(CK)
I2S clock rise time
Capacitive load CL=30pF
-
8
ns
t
f(CK)
I2S clock fall time
8
t
v(WS)
WS valid time
Master mode
4
24
t
h(WS)
WS hold time
Master mode
0
-
t
su(WS)
WS setup time
Slave mode
15
-
t
h(WS)
WS hold time
Slave mode
0
-
t
su(SD_MR)
Data input setup time
Master receiver
8
-
t
su(SD_SR)
Data input setup time
Slave receiver
9
-
t
h(SD_MR)
Data input hold time
Master receiver
5
-
t
h(SD_SR)
Slave receiver
4
-
t
v(SD_ST)
Data output valid time
Slave transmitter
(after enable edge)
-
64
t
h(SD_ST)
Data output hold time
Slave transmitter
(after enable edge)
22
-
t
v(SD_MT)
Data output valid time
Master transmitter
(after enable edge)
-
12
t
h(SD_MT)
Data output hold time
Master transmitter
(after enable edge)
8
-
Table 53. USB: full speed electrical characteristics (continued)
Driver characteristics
(1)
Symbol
Parameter
Conditions
Min
Max
Unit
