Functional overview
STM32L162VC, STM32L162RC
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DocID022881 Rev 10
The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded ARM core, the STM32L162xC devices are compatible with all ARM
tools and software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L162xC devices embed a nested vectored interrupt controller
able to handle up to 53 maskable interrupt channels (not including the 16 interrupt lines of
ARM
®
Cortex
®
-M3) and 16 priority levels.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Closely coupled NVIC core interface
•
Allows early processing of interrupts
•
Processing of
late arriving
, higher-priority interrupts
•
Support for tail-chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.3
Reset and supply management
3.3.1
Power supply schemes
•
V
DD
= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through V
DD
pins.
•
V
SSA
, V
DDA
= 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to V
DDA
is 1.8 V when the ADC is used). V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively.
3.3.2
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
•
The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
•
The other version without BOR operates between 1.65 V and 3.6 V.
After the V
DD
threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the V
DD
min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
