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STM32F042x4 STM32F042x6
Functional overview
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from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C peripheral can be served by the DMA controller.
3.15 Universal
synchronous/asynchronous receiver/transmitter
(USART)
The device embeds two universal synchronous/asynchronous receivers/transmitters
(USART1, USART2) which communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
half-duplex communication mode. USART1 supports also SmartCard communication (ISO
7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and has a
clock domain independent of the CPU clock, allowing to wake up the MCU from Stop mode.
The USART interfaces can be served by the DMA controller.
Table 9. STM32F042x4/x6 I
2
C implementation
I
2
C features
(1)
1. X = supported.
I2C1
7-bit addressing mode
X
10-bit addressing mode
X
Standard mode (up to 100 kbit/s)
X
Fast mode (up to 400 kbit/s)
X
Fast Mode Plus with
20 mA output drive I/Os (up to 1 Mbit/s)
X
Independent clock
X
SMBus
X
Wakeup from STOP
X
Table 10. STM32F042x4/x6 USART implementation
USART modes/features
(1)
USART1
USART2
Hardware flow control for modem
X
X
Continuous communication using DMA
X
X
Multiprocessor communication
X
X
Synchronous mode
X
X
Smartcard mode
X
-
Single-wire half-duplex communication
X
X
IrDA SIR ENDEC block
X
-
LIN mode
X
-
Dual clock domain and wakeup from Stop mode
X
-
Receiver timeout interrupt
X
-
