1 Intro
2
Electrocardiogram (
Ecg
) Signals
The Electrocardiogram (
Ecg
)
•
Ecg
: electrical manifestation of heart activity recorded
from the body surface
•
monitoring of heart rate
The
Ecg
signal can be recorded fairly easily with surface
electrodes placed on the limbs and/or the chest, see pages
6
–
16
below.
Josef Goette
2
2009
2 System Description
2.3.2 Cortex
The new generation of processors comes as complete processor core that provides a standard CPU
and system architecture.
On the ARM7 systems every manufacturer had to add the basic peripherals like interrupt con-
troller, systick timer and sleep modes. This has now been built into the Cortex-M3 core. The
Cortex-M3 provides a standardized microcontroller core which goes beyond the classical CPU to
provide the entire heart of a microcontroller (including the interrupt system, 24-bit SysTick timer,
debug system and memory map).
The Cortex family comes in three main profiles: The
A
profile for
high end applications (applications processors for complex OS and
user applications),
R
for real time and
M
for cost-sensitive and mi-
crocontroller applications.
The STM32 is based on the Cortex-M3 profile, which is specifically designed for high system
performance combined with low power consumption. It has a low enough cost to challenge tra-
ditional 8 and 16-bit microcontrollers.
The Cortex-M3 is a Harvard architecture (Code and Databus are separated) and has multiple buses
that allow it to perform operations in parallel. The architecture inside the Cortex-M3 is a ARMv7-
M RISC processor.
With only 33’000 logic cells needed to syntetisize the M3 core it is the smallest core of the ARM
family. This reduces the size of the chip and therefore cheap manufacturing processes with 0.35
µ
m can be used.
Interrupts
One of the key components of the Cortex-M3 core is the
Nested Vector Interrupt Controller
(NVIC).
The NVIC provides a standard interrupt structure for all Cortex based microcontrollers and excep-
tional interrupt handling. The NVIC provides dedicated interrupt vectors for up to 240 peripheral
sources where each interrupt source can be individually prioritized. The NVIC provide extremely
fast interrupt handling. The time taken from receiving an interrupt to reaching the first line of
code in your interrupt service routine is just twelve cycles.
All interrupts can be prioritized on three levels: pre-empting, sub-priority and hardware-priority.
The first two can be configured via the software and the priority can be set on 4 bits.
The interrupt service routines (ISR) can be written fully in C, therefore no Assembler is needed
any more.
Instruction Set
While the ARM7 and ARM9 CPUs have two instruction sets (the 32-bit ARM and the 16-bit
Thumb), the Cortex family is designed to support only the 16-bit Thumb-2 instruction set. The
result is a simpler assembling of the core since there is not longer need for switching between the
two instruction sets. The Thumb-2 instruction set is a rich instruction set that is designed as a
target for C/C++ compilers.
4
STM32 Cortex-M3 Tutorial
