ST10 FAMILY PROGRAMMING MANUAL
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EXTR
Begin EXTended Register Sequence
Syntax
EXTR op1
Operation
(count)
<-- (op1) [1
≤
op1
≤
4]
Disable interrupts and Class A traps
SFR_range = Extended
DO WHILE ((count)
≠
0 AND Class_B_trap_condition
≠
TRUE)
Next Instruction
(count)
<-- (count) - 1
END WHILE
(count) = 0
SFR_range = Standard
Enable interrupts and traps
Description
Causes all SFR or SFR bit accesses via the “reg”, “bitoff” or “bitaddr” addressing modes being made to
the Extended SFR space for a specified number of instructions. During their execution, both standard and
PEC interrupts and class A hardware traps are locked.
The value of op1 defines the length of the effected instruction sequence.
Note: The EXTR instruction must be used carefully (see Section 2.7 - ATOMIC and EXTended instruc-
tions on page 38).
Flags
Addressing Modes
E
Z
V
C
N
-
-
-
-
-
E
Not affected
Z
Not affected
V
Not affected
C
Not affected
N
Not affected
Mnemonic
Format
Bytes
EXTR
#data
2
D1 10##:0
2
Summary of Contents for ST10 Series
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