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ST10 FAMILY PROGRAMMING MANUAL

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BCLR

Bit Clear

Syntax

BCLR op1

Operation

(op1) <--

Data Types

BIT

Description

Clears the bit specified by op1. This instruction is primarily used for peripheral and system control.

Flags

Addressing Modes

Always cleared.

Contains the logical negation of the previous state of the specified bit.

Always cleared.

Contains the previous state of the specified bit.

Mnemonic

Format

Bytes

BCLR

bitaddr

Q.q

qE QQ

Summary of Contents for ST10 Series

Page 1: ...This is advance information on a new product now in development or undergoing evaluation Details are subject to change without notice Ref ST10FPM ST10 FAMILY PROGRAMMING MANUAL...

Page 2: ......

Page 3: ...OPCODES 26 2 6 INSTRUCTION CONVENTIONS 34 2 6 1 Instruction name 34 2 6 2 Syntax 34 2 6 3 Operation 34 2 6 4 Data types 35 2 6 5 Description 35 2 6 6 Condition code 35 2 6 7 Flags 36 2 6 8 Addressing...

Page 4: ...ST10 FAMILY PROGRAMMING MANUAL 2 172...

Page 5: ...ordered by hexadecimal opcode can be used to identify specific instructions when reading executable code i e during the de bugging phase Finally each instruction is described individually on a page o...

Page 6: ...significant for physical address generation therefore it can be regarded as identical to the address generation described for the Rb and Rw addressing modes bitoff Specifies direct access to any word...

Page 7: ...t are concatenated with the 14 bit data page offset to build the physi cal address Note Word accesses on odd byte addresses are not executed but rather trigger a hardware trap After reset the DPP regi...

Page 8: ...address pointers are speci fied by short 2 bit addresses Word accesses on odd byte addresses are not executed but rather trigger a hardware trap After reset the DPP registers are initialized in a way...

Page 9: ...nd trap jump vector table situated in the lowest portion of code segment 0 Table 3 Table of indirect address modes Mnemonic Notes Rw Most instructions accept any GPR R15 R0 as indirect address pointer...

Page 10: ...Ch in code segment 0 i e the interrupt jump vector table For further information on the relation between trap numbers and interrupt or trap sources refer to the device user manual section on Interrupt...

Page 11: ...us modes state times plus a number of state times which is determined by the number of waitstates programmed in the MCTC Memory Cycle Time Control and MTTC Memory Tristate Time Control bit fields of t...

Page 12: ...RAM TImin ROM 4 States For 4 byte instructions TImin RAM TImin ROM 6 States Unlike internal ROM program execution the mini mum time TImin ext to process an external instruction also depends on instru...

Page 13: ...the extra state times can be avoided by putting other suitable instructions before the instruction In 1 reading the SFR External operand reads TIadd 1 ACT Any external operand reading via a 16 bit wid...

Page 14: ...ddresses xxx0h xxx4h xxx8h xxxCh Testing Branch Conditions TIadd 0 or 1 States NO extra time is usually required for a conditional branch instructions to decide whether a branch condi tion is met or n...

Page 15: ...BITadd ORB OR ORB OR ORB OR ORB OR ORB OR 8x _ _ JB MOVB MOV IDLE CMPI1 _ MOV CoXXX CMPI NEG CMPI1 BITadd REL Rw m Rw n Rw n d 16 Rw n MEM Rw n Rw m Rw n MEM Rw n Rw n d 4 9x JMPI TRAP MOVB MOV PWRDN...

Page 16: ...B mem reg 4 MUL Rwn Rwm 2 MULU ASHR Rwn Rwm 2 CMPD1 2 Rwn data4 2 ROL ROR Rwn data4 2 CMPI1 2 Rwn data16 4 SHL SHR Rwn mem 4 BAND bitaddrZ z bitaddrQ q 4 CMP B Rwn Rwm 1 BCMP Rwn Rwi 1 2 BMOV Rwn Rwi...

Page 17: ...n the bit addressable memory area bitoff Direct word in the bit addressable mem ory area datax Immediate constant the number of signif icant bits that can be user specified is given by the appendix x...

Page 18: ...12 4 ADD reg mem Add direct word memory to direct register 2 8 4 6 8 12 4 ADD mem reg Add direct word register to direct memory 2 8 4 6 8 12 4 ADDB Rb Rb Add direct byte GPR to direct GPR 2 6 2 3 4 6...

Page 19: ...by direct GPR 16 16 bit 10 14 10 11 12 14 2 MULU Rw Rw Unsigned multiply direct GPR by direct GPR 16 16 bit 10 14 10 11 12 14 2 NEG Rw Negate direct word GPR 2 6 2 3 4 6 2 NEGB Rb Negate direct byte...

Page 20: ...Rb data3 Subtract immediate byte data from direct GPR with Carry 2 6 2 3 4 6 2 SUBCB reg data16 Subtract immediate byte data from direct register with Carry 2 8 4 6 8 12 4 SUBCB reg mem Subtract dire...

Page 21: ...GPR 2 6 2 3 4 6 2 ORB reg data16 Bitwise OR immediate byte data with direct register 2 8 4 6 8 12 4 ORB reg mem Bitwise OR direct byte memory with direct register 2 8 4 6 8 12 4 ORB mem reg Bitwise O...

Page 22: ...SET bitaddr Set direct bit 2 6 2 3 4 6 2 BXOR bitaddr bitaddr XOR direct bit with direct bit 2 8 4 6 8 12 4 CMP Rw Rw Compare direct word GPR to direct GPR 2 6 2 3 4 6 2 CMP Rw Rw Compare indirect wor...

Page 23: ...word memory to direct GPR and decrement GPR by 2 2 8 4 6 8 12 4 CMPI1 Rw data4 Compare immediate word data to direct GPR and increment GPR by 1 2 6 2 3 4 6 2 CMPI1 Rw data16 Compare immediate word da...

Page 24: ...es specified by immediate data 2 6 2 3 4 6 2 SHR Rw Rw Shift right direct word GPR number of shift cycles specified by direct GPR 2 6 2 3 4 6 2 SHR Rw data4 Shift right direct word GPR number of shift...

Page 25: ...to indirect memory and post increment destination pointer by 1 2 6 2 3 4 6 2 MOVB Rw Rw Move indirect byte memory to indirect memory and post increment source pointer by 1 2 6 2 3 4 6 2 MOVB Rb Rw da...

Page 26: ...bit is not set 4 10 6 8 10 14 4 JNBS bitaddr rel Jump relative and set bit if direct bit is not set 4 10 6 8 10 14 4 PCALL reg caddr Push direct word register onto system stack and call absolute subro...

Page 27: ...6 8 12 4 EXTPR Rw data2 Begin EXTended Page and Register sequence 1 2 6 2 3 4 6 2 EXTPR pag data2 Begin EXTended Page and Register sequence 1 2 8 4 6 8 12 4 EXTS Rw data2 Begin EXTended Segment sequen...

Page 28: ...on the BCLR and BSET instructions The position of the bit to be set or to be cleared is specified by the opcode The operand bitaddrQ q where q 0 to 15 refers to a particular bit within a bit addressab...

Page 29: ...SET bitaddrQ 1 20 2 SUB Rwn Rwm 21 2 SUBB Rbn Rbm 22 4 SUB reg mem 23 4 SUBB reg mem 24 4 SUB mem reg 25 4 SUBB mem reg 26 4 SUB reg data16 27 4 SUBB reg data16 28 2 SUB Rwn Rwi or Rwn Rwi or Rwn data...

Page 30: ...Q 3 40 2 CMP Rwn Rwm 41 2 CMPB Rbn Rbm 42 4 CMP reg mem 43 4 CMPB reg mem 44 45 46 4 CMP reg data16 47 4 CMPB reg data16 48 2 CMP Rwn Rwi or Rwn Rwi or Rwn data3 49 2 CMPB Rbn Rwi or Rbn Rwi or Rbn da...

Page 31: ...m 63 4 ANDB reg mem 64 4 AND mem reg 65 4 ANDB mem reg 66 4 AND reg data16 67 4 ANDB reg data16 68 2 AND Rwn Rwi or Rwn Rwi or Rwn data3 69 2 ANDB Rbn Rwi or Rbn Rwi or Rbn data3 6A 4 BAND bitaddrZ z...

Page 32: ...CMPI1 Rwn mem 83 4 CoXXX1 Rwn Rwm 84 4 MOV Rwn mem 85 86 4 CMPI1 Rwn data16 87 4 IDLE 88 2 MOV Rwm Rwn 89 2 MOVB Rwm Rbn 8A 4 JB bitaddrQ q rel 8B 8C 8D 2 JMPR cc_C rel or cc_ULT rel 8E 2 BCLR bitadd...

Page 33: ...data16 A7 4 SRVWDT A8 2 MOV Rwn Rwm A9 2 MOVB Rbn Rwm AA 4 JBC bitaddrQ q rel AB 2 CALLI cc Rwn AC 2 ASHR Rwn Rwm AD 2 JMPR cc_SGT rel AE 2 BCLR bitaddrQ 10 AF 2 BSET bitaddrQ 10 B0 2 CMPD2 Rwn data4...

Page 34: ...CA 4 CALLA cc caddr CB 2 RET CC 2 NOP CD 2 JMPR cc_SLT rel CE 2 BCLR bitaddrQ 12 CF 2 BSET bitaddrQ 12 D0 2 MOVBS Rbn Rbm D1 2 ATOMIC EXTR data2 D2 4 MOVBS reg mem D3 4 CoMOV1 IDXi Rwn D4 4 MOV Rwn R...

Page 35: ...MOV Rwn Rwm E9 2 MOVB Rwn Rwm EA 4 JMPA cc caddr EB 2 RETP reg EC 2 PUSH reg ED 2 JMPR cc_UGT rel EE 2 BCLR bitaddrQ 14 EF 2 BSET bitaddrQ 14 F0 2 MOV Rwn Rwm F1 2 MOVB Rbn Rbm F2 4 MOV reg mem F3 4 M...

Page 36: ...opX is used as pointer to the actual operand The following abbreviations are used to describe operands Table 22 Instruction operation symbols Diadic operations operator opY opx opy opY is MOVED into...

Page 37: ...able summarizes the 16 possible condition codes that can be used within Call and Branch instructions and shows the mnemonic abbreviations the test executed for a specific con dition and the 4 bit cond...

Page 38: ...e flag is set according to the following standard rules N 1 Most significant bit of the result is set N 0 Most significant bit of the result is not set C 1 Carry occurred during operation C 0 No Carry...

Page 39: ...rmat N nibble 4 bits The following sym bols are used to describe the instruction for mats Table 26 Instruction format symbols 00h through FFh Instruction Opcodes 0 1 Constant Values Each of the 4 char...

Page 40: ...n this sense Any instruction type can be used with the ATOMIC and EXTended instruc tions CAUTION When a Class B trap interrupts an ATOMIC or EXTended sequence this sequence is terminated the interrupt...

Page 41: ...he value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurre...

Page 42: ...leared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in the specified data typ...

Page 43: ...epresents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and previous Z flag was set Cleared otherwise V Set if an arithmetic overf...

Page 44: ...resents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and previous Z flag was set Cleared otherwise V Set if an arithmetic overflo...

Page 45: ...g Modes E Z V C N 0 0 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Alway...

Page 46: ...odes E Z V C N 0 0 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always c...

Page 47: ...ignificant bit was a 1 The Overflow flag is used as a Rounding flag The least significant bit is shifted into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count con...

Page 48: ...at no additional NOPs are required Depending on the value of op1 the period of validity of the ATOMIC sequence extends over the sequence of the next 1 to 4 instructions being executed after the ATOMIC...

Page 49: ...estination bit specified by op1 The result is then stored in op1 Flags Addressing Modes E Z V C N 0 NOR OR AND XOR E Always cleared Z Contains the logical NOR of the two specified bits V Contains the...

Page 50: ...op1 This instruction is primarily used for peripheral and system control Flags Addressing Modes E Z V C N 0 B 0 0 B E Always cleared Z Contains the logical negation of the previous state of the speci...

Page 51: ...ied by operand op2 No result is written by this instruction Only the flags are updated Flags Addressing Modes E Z V C N 0 NOR OR AND XOR E Always cleared Z Contains the logical NOR of the two specifie...

Page 52: ...ith the bits at the corresponding positions in the OR mask specified by op3 Note Bits which are masked off by a 0 in the AND mask op2 may be unintentionally altered if the corre sponding bit in the OR...

Page 53: ...h the bits at the corresponding positions in the OR mask specified by op3 Note Bits which are masked off by a 0 in the AND mask op2 may be unintentionally altered if the corre sponding bit in the OR m...

Page 54: ...to the destination operand specified by op1 The source bit is examined and the flags are updated accordingly Flags Addressing Modes E Z V C N 0 B 0 0 B E Always cleared Z Contains the logical negation...

Page 55: ...ied by op2 into the destination oper and specified by op1 The source bit is examined and the flags are updated accordingly Flags Addressing Modes E Z V C N 0 B 0 0 B E Always cleared Z Contains the lo...

Page 56: ...ination bit speci fied by operand op1 The ORed result is then stored in op1 Flags Addressing Modes E Z V C N 0 NOR OR AND XOR E Always cleared Z Contains the logical NOR of the two specified bits V Co...

Page 57: ...p1 This instruction is primarily used for peripheral and system control Flags Addressing Modes E Z V C N 0 B 0 0 B E Always cleared Z Contains the logical negation of the previous state of the specifi...

Page 58: ...destina tion bit specified by operand op1 The XORed result is then stored in op1 Flags Addressing Modes E Z V C N 0 NOR OR AND XOR E Always cleared Z Contains the logical NOR of the two specified bit...

Page 59: ...ction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of...

Page 60: ...uction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack rep resents the return address o...

Page 61: ...e value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack rep resents...

Page 62: ...the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address to the calling routine The previous...

Page 63: ...Z V C N S E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithme...

Page 64: ...C N S E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic...

Page 65: ...sing the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range Flags Addressing Modes E Z V C N S E Set if the...

Page 66: ...sing the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range Flags Addressing Modes E Z V C N S E Set if the...

Page 67: ...sing the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range Flags Addressing Modes E Z V C N S E Set if the...

Page 68: ...sing the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range Flags Addressing Modes E Z V C N S E Set if the...

Page 69: ...p1 The result is stored back into op1 Flags Addressing Modes E Z V C N 0 0 E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table...

Page 70: ...p1 The result is stored back into op1 Flags Addressing Modes E Z V C N 0 0 E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table...

Page 71: ...ction Following a reset this instruction can be executed at any time until either a Service Watchdog Timer instruction SRVWDT or an End of Initialization instruction EINIT are executed Once one of the...

Page 72: ...ored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH Flags Addressing Modes E Z V C N 0 S 0 E Always cleared Z Set if result equa...

Page 73: ...then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH Flags Addressing Modes E Z V C N 0 S 0 E Always cleared Z Set if res...

Page 74: ...is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH Flags Addressing Modes E Z V C N 0 S 0 E Always cleared Z Set if...

Page 75: ...stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH Flags Addressing Modes E Z V C N 0 S 0 E Always cleared Z Set if result e...

Page 76: ...ted at which time it goes high This enables the program to signal the external circuitry that it has successfully initial ized the microcontroller After the EINIT instruction has been executed executi...

Page 77: ...TP instruction becomes immediately active such that no additional NOPs are required For any long mem or indirect address in the EXTP instruction sequence the 10 bit page number address bits A23 A14 is...

Page 78: ...specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked For any long mem or indirect address in the EXTP instruction sequence the...

Page 79: ...accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class A...

Page 80: ...re locked The EXTS instruction becomes immediately active such that no additional NOPs are required For any long mem or indirect address in an EXTS instruction sequence the value of op1 deter mines th...

Page 81: ...ions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTSR instruction becomes immediately active such that no additional NOPs are required For any lo...

Page 82: ...powered down while the peripherals remain running It remains powered down until a peripheral interrupt or external interrupt occurs To insure that this instruction is not accidentally executed it is...

Page 83: ...cified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calcu lation is th...

Page 84: ...maphore operations The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the addr...

Page 85: ...is met a branch to the absolute address specified by op2 is taken If the condition is not met no action is taken and the instruction following the JMPA instruction is executed nor mally Condition Code...

Page 86: ...op1 is met a branch to the absolute address specified by op2 is taken If the condition is not met no action is taken and the instruction following the JMPI instruction is executed nor mally Condition...

Page 87: ...s a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the...

Page 88: ...ration CSP op1 IP op2 Description Branches unconditionally to the absolute address specified by op2 within the segment specified by op1 Flags Addressing Modes E Z V C N E Not affected Z Not affected V...

Page 89: ...pecified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calcu lation is...

Page 90: ...ma phore operations The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the add...

Page 91: ...ared otherwise Used to signal the end of a table Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the sourc...

Page 92: ...herwise Used to signal the end of a table Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the source opera...

Page 93: ...o the word location specified by the destination operand op1 The contents of the moved data is examined and the flags are updated accordingly Flags Addressing Modes E Z V C N 0 E Always cleared Z Set...

Page 94: ...d by op2 to the word location specified by the destination operand op1 The contents of the moved data is examined and the flags are updated accordingly Flags Addressing Modes E Z V C N 0 0 E Always cl...

Page 95: ...perands op1 and op2 respectively The signed 32 bit result is placed in the MD register Flags Addressing Modes E Z V C N 0 S 0 E Always cleared Z Set if the result equals zero Cleared otherwise V This...

Page 96: ...operands op1 and op2 respectively The unsigned 32 bit result is placed in the MD register Flags Addressing Modes E Z V C N 0 S 0 E Always cleared Z Set if the result equals zero Cleared otherwise V Th...

Page 97: ...V C N S E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmeti...

Page 98: ...V C N S E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmeti...

Page 99: ...peration Description This instruction causes a null operation to be performed A null operation causes no change in the status of the flags Flags Addressing Modes E Z V C N E Not affected Z Not affecte...

Page 100: ...ing Modes E Z V C N 0 0 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Alw...

Page 101: ...g Modes E Z V C N 0 0 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Alway...

Page 102: ...IP always points to the instruction following the branch instruction the value stored on the system stack rep resents the return address of the calling routine Flags Addressing Modes E Z V C N E Set i...

Page 103: ...d by op1 The Stack Pointer is then incremented by two Flags Addressing Modes E Z V C N E Set if the value of the popped word represents the lowest possible negative number Cleared otherwise Used to si...

Page 104: ...ified by op1 indicating the number of single bit shifts required to normalize the operand op2 so that its most significant bit is equal to one If the source operand op2 equals zero a zero is written t...

Page 105: ...tack Pointer after the Stack Pointer has been decremented by two Flags Addressing Modes E Z V C N E Set if the value of the pushed word represents the lowest possible negative number Cleared otherwise...

Page 106: ...xternally reset To insure that this instruction is not accidentally exe cuted it is implemented as a protected instruction To further control the action of this instruction the PWRDN instruction is on...

Page 107: ...ription Returns from a subroutine The IP is popped from the system stack Execution resumes at the instruction following the CALL instruction in the calling routine Flags Addressing Modes E Z V C N E N...

Page 108: ...uction which had been interrupted The previous system state is restored after the PSW has been popped The CSP is only popped if segmentation is enabled This is indicated by the SGTDIS bit in the SYSCO...

Page 109: ...Execution resumes at the instruction following the CALL instruction in the calling routine Flags Addressing Modes E Z V C N E Set if the value of the word popped into operand op1 represents the lowest...

Page 110: ...escription Returns from an inter segment subroutine The IP and CSP are popped from the system stack Execution resumes at the instruction following the CALLS instruction in the calling routine Flags Ad...

Page 111: ...it 0 and into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used Flags Addressing Modes E Z V C N 0 0 S E Always...

Page 112: ...tween 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used Flags Addressing Modes E Z V C N 0 S S E Always cleared Z Set if result equals zero Cleared...

Page 113: ...r Switching context is a push and load operation The contents of the register specified by the first operand op1 are pushed onto the stack That register is then loaded with the value specified by the...

Page 114: ...ccordingly The most significant bit is shifted into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used Flags Addr...

Page 115: ...lag helps the user to determine whether the remainder bits lost were greater than less than or equal to one half an least significant bit Only shift values between 0 and 15 are allowed When using a GP...

Page 116: ...re reset has the same effect on the micro controller as an externally applied hardware reset To insure that this instruction is not accidentally exe cuted it is implemented as a protected instruction...

Page 117: ...tchdog Timer with a preset value and clears the low byte on every occurrence Once this instruction has been executed the watchdog timer cannot be disabled To insure that this instruction is not accide...

Page 118: ...the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be...

Page 119: ...e lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred ie the result cannot be re...

Page 120: ...N S S E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and the previous Z flag was set Cleared o...

Page 121: ...S S E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and the previous Z flag was set Cleared oth...

Page 122: ...tine has no indication of whether it was called by software or hardware System state is preserved identically to hardware interrupt entry except that the CPU priority level is not affected The RETI re...

Page 123: ...Addressing Modes E Z V C N 0 0 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwis...

Page 124: ...ressing Modes E Z V C N 0 0 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V...

Page 125: ...be a legal address even if its content is not modified An odd value e g in R0 when using R0 post modification adressing mode will trigger the class B hardware Trap 28h Illegal Word Operand Access Trap...

Page 126: ...oMULsu CoMACMsu CoMUL CoMACM CoMULu CoMACMu CoMULus CoMACMus CoMULsu CoMACMsu CoMUL rnd CoMACM rnd CoMULu rnd CoMACMu rnd CoMULus rnd CoMACMus rnd CoMULsu rnd CoMACMsu rnd CoMAC Rwn Rwm No CoMACMR CoM...

Page 127: ...1 CoMACMu rnd 19 CoMULus rnd 81 CoMACMus rnd 99 CoMULsu rnd 41 CoMACMsu rnd 59 CoMAC D0 CoMACMR F9 CoMACu 10 CoMACMRu 38 CoMACus 90 CoMACMRus B8 CoMACsu 50 CoMACMRsu 78 CoMAC E0 CoMACMR rnd F9 CoMACu...

Page 128: ...COMPARED against opX opX opY opX is CONCATANATED to opY LSW Max opX opY MAXIMUM value between opX and opY Min opX opY MINIMUM value between opX and opY Monadic Operations opX opX is Logically SHIFTED...

Page 129: ...ons on page 126 for detailed information about the instruction con ventions The MAC instruction set is divided into 5 functional groups Multiply and Multiply Accumulate Instructions 40 bit Arithmetic...

Page 130: ...operand results from the con catenation of the two source operands op1 LSW and op2 MSW which is then sign extended This instruction is not repeatable MAC Flags Addressing Modes N Z C SV E SL 0 N Set i...

Page 131: ...00h respectively This instruction is repeatable with indirect addressing modes and allows up to two parallel memory reads MAC Flags Note The E flag is set when the nine highest bits of the accumulator...

Page 132: ...4000h 7F BFFF FFFFh 7F FFFF FFFFh 0 0 0 1 CoADD 0 0001h 4000h 7F BFFF FFFFh 80 0000 0000h 1 0 0 1 1 CoADD 0 FFFFh FFFFh FF FFFF FFFFh FF FFFF FFFEh 1 0 1 0 CoADD 0 FFFFh FFFFh 00 0000 0001h 00 0000 00...

Page 133: ...on the MS bit of the MCW register does not affect the result While with rnd option and if the MS bit is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFFh or...

Page 134: ...of the MCW register does not affect the result This instruction is not repeatable and allows up to two parallel memory reads MAC Flags Addressing Modes Examples N Z C SV E SL N Set if the most signif...

Page 135: ...s set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFFh or FF 8000 0000h respectively This instruction is not repeatable and allows up to two parallel memory rea...

Page 136: ...0000 8000h END IF MAL 0 Data Types DOUBLE WORD Result 40 bit signed value Description Multiplies the two signed 16 bit source operands op1 and op2 The obtained signed 32 bit product is first sign ext...

Page 137: ...wm No A3 nm F0 00 4 CoMACR Rwn Rwm rnd No A3 nm F1 00 4 CoMAC IDXi Rwm Yes 93 Xm D0 rrrr rqqq 4 CoMAC IDXi Rwm Yes 93 Xm E0 rrrr rqqq 4 CoMAC IDXi Rwm rnd Yes 93 Xm D1 rrrr rqqq 4 CoMACR IDXi Rwm Yes...

Page 138: ...is optionally rounded before being stored in the 40 bit ACC register The result is never affected by the MP mode flag contained in the MCW register option is used to negate the specified product R opt...

Page 139: ...Xi Rwm Yes 93 Xm 30 rrrr rqqq 4 CoMACRu IDXi Rwm rnd Yes 93 Xm 31 rrrr rqqq 4 CoMACu Rwn Rwm Yes 83 nm 10 rrrr rqqq 4 CoMACu Rwn Rwm Yes 83 nm 20 rrrr rqqq 4 CoMACu Rwn Rwm rnd Yes 83 nm 11 rrrr rqqq...

Page 140: ...tained result is optionally rounded before being stored in the 40 bit ACC register The result is never affected by the MP mode flag contained in the MCW register option is used to negate the specified...

Page 141: ...Rwm Yes 93 Xm B0 rrrr rqqq 4 CoMACRus IDXi Rwm rnd Yes 93 Xm B1 rrrr rqqq 4 CoMACus Rwn Rwm Yes 83 nm 90 rrrr rqqq 4 CoMACus Rwn Rwm Yes 83 nm A0 rrrr rqqq 4 CoMACus Rwn Rwm rnd Yes 83 nm 91 rrrr rqq...

Page 142: ...tained result is optionally rounded before being stored in the 40 bit ACC register The result is never affected by the MP mode flag contained in the MCW register option is used to negate the specified...

Page 143: ...Xi Rwm Yes 93 Xm 70 rrrr rqqq 4 CoMACRsu IDXi Rwm rnd Yes 93 Xm 71 rrrr rqqq 4 CoMACsu Rwn Rwm Yes 83 nm 50 rrrr rqqq 4 CoMACsu Rwn Rwm Yes 83 nm 60 rrrr rqqq 4 CoMACsu Rwn Rwm rnd Yes 83 nm 51 rrrr r...

Page 144: ...CC ACC tmp 00 0000 8000h ELSE tmp op1 op2 ACC ACC tmp 00 0000 8000h END IF MAL 0 IDXi IDXi Syntax CoMACM op1 op2 Operation IF MP 1 THEN tmp op1 op2 1 ACC ACC tmp ELSE tmp op1 op2 ACC ACC tmp END IF ID...

Page 145: ...parallel mem ory reads In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memory DPRAM The address of the overwritten...

Page 146: ...QR1 rnd ACC ACC IDX1 R10 rnd R10 R10 QR1 IDX1 QX0 IDX1 IDX1 IDX1 QX0 Repeat 3 times CoMACM CoMACM IDX0 QX0 R8 QR0 ACC ACC IDX0 R8 R8 R8 QR0 IDX0 QX0 IDX0 IDX0 IDX0 QX0 Repeat MRW times CoMACM CoMACM I...

Page 147: ...ded subtracted to from the 40 bit ACC register content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register option is used to negate the specified product R...

Page 148: ...f the ACC is automatically saturated Not affected otherwise Mnemonic Rep Format Bytes CoMACMu IDXi Rwm Yes 93 Xm 18 rrrr rqqq 4 CoMACMu IDXi Rwm Yes 93 Xm 28 rrrr rqqq 4 CoMACMu IDXi Rwm rnd Yes 93 Xm...

Page 149: ...eing added subtracted to from the 40 bit ACC regis ter content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register option is used to negate the specified p...

Page 150: ...is automatically saturated Not affected otherwise Mnemonic Rep Format Bytes CoMACMus IDXi Rwm Yes 93 Xm 98 rrrr rqqq 4 CoMACMus IDXi Rwm Yes 93 Xm A8 rrrr rqqq 4 CoMACMus IDXi Rwm rnd Yes 93 Xm 99 rr...

Page 151: ...ing added subtracted to from the 40 bit ACC regis ter content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register option is used to negate the specified pr...

Page 152: ...tically saturated Not affected otherwise Mnemonic Rep Format Bytes CoMACMsu IDXi Rwm Yes 93 Xm 58 rrrr rqqq 4 CoMACMsu IDXi Rwm Yes 93 Xm 68 rrrr rqqq 4 CoMACMsu IDXi Rwm rnd Yes 93 Xm 59 rrrr rqqq 4...

Page 153: ...e MS bit of the MCW register does not affect the result This instruction is repeatable with indirect addressing modes MAC Flags Addressing Modes Examples N Z C SV E SL 0 N Set if the most significant...

Page 154: ...e MS bit of the MCW register does not affect the result This instruction is repeatable with indirect addressing modes MAC Flags Addressing Modes Examples N Z C SV E SL 0 N Set if the most significant...

Page 155: ...od ify the CPU Flags as any other MOV instruction CPU Flags MAC Flags Addressing Modes Examples E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Use...

Page 156: ...ted and finally it is optionally either negated or rounded before being stored in the 40 bit ACC register The option is used to negate the specified product while the rnd option is used to round the p...

Page 157: ...1 rnd CoMUL R2 R6 ACC R2 R6 R6 R6 2 CoMUL IDX0 QX1 R11 ACC IDX0 R11 R11 R11 2 IDX0 IDX0 QX1 CoMUL IDX1 R15 QR0 ACC IDX1 R15 R15 R15 QR0 IDX1 IDX1 2 CoMUL IDX1 QX0 R9 QR1 rnd ACC IDX1 R9 rnd R9 R9 QR1...

Page 158: ...e rnd option is used to round the product using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically clea...

Page 159: ...11 ACC IDX0 R11 R11 R11 2 CoMULu IDX1 R15 QR0 ACC IDX1 R15 R15 R15 QR0 IDX1 IDX1 2 CoMULu IDX0 QX0 R9 rnd ACC IDX0 R9 rnd R9 R9 2 IDX0 IDX0 QX0 Cases op 1 op 2 rnd MAE MAH MAL N Z C SV E SL MP x MS x...

Page 160: ...roduct while the rnd option is used to round the product using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is aut...

Page 161: ...R11 R11 R11 QR0 IDX1 IDX1 QX0 CoMULus IDX0 R15 ACC IDX0 R15 CoMULus IDX0 QX0 R9 QR1 rnd ACC IDX0 R9 rnd R9 R9 QR1 IDX0 IDX0 QX0 Cases op 1 op 2 rnd MAE MAH MAL N Z C SV E SL MP x MS x 8000h 8000h x FF...

Page 162: ...roduct while the rnd option is used to round the product using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is aut...

Page 163: ...1 R11 R11 2 CoMULsu IDX1 R15 ACC IDX1 R15 IDX1 IDX1 2 CoMULsu IDX0 QX0 R9 QR1 rnd ACC IDX0 R9 rnd R9 R9 QR1 IDX0 IDX0 QX0 Cases op 1 op 2 rnd MAE MAH MAL N Z C SV E SL MP x MS x 8000h 8000h x FFh C000...

Page 164: ...esult becomes 00 7FFF FFFFh or FF 8000 0000h respectively This instruction is not repeatable MAC Flags Addressing Modes Examples N Z C SV E SL N Set if the m s b of the result is set Cleared otherwise...

Page 165: ...address pointers without changing the internal MAC Unit registers MAC Flags Addressing Modes Example N Z C SV E SL N Not affected Z Not affected C Not affected SV Not affected E Not affected SL Not af...

Page 166: ...w occurs the obtained result becomes 00 7FFF FFFFh or FF 8000 0000h respectively This instruction is not repeatable MAC Flags Addressing Modes Notes CoRND is equivalent to CoASHR 0 rnd Example N Z C S...

Page 167: ...the MCW register is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFFh or FF 8000 0000h respectively This instruction is repeatable when op1 is not an immedia...

Page 168: ...ta or the least significant 5 bits considered as unsigned data of any register directly or indirectly addressed operand The MS bit of the MCW register does not affect the result This instruction is re...

Page 169: ...AC Flags Addressing Modes Note Due to pipeline side effects CoSTORE cannot be directly followed by a MOV instruction the source operand of which is also a MAC Unit register such as MSW MAH MAL MAS MRW...

Page 170: ...so multiplied by 2 prior to being subtracted added from to the ACC negated ACC When the most significant bit of the MCW register is set and when a 32 bit overflow or underflow occurs the obtained resu...

Page 171: ...m 52 rrrr rqqq 4 CoSUB R0 R1 ACC ACC R1 R0 CoSUB2 R2 R6 ACC ACC 2 R6 R2 R6 R6 2 Repeat 3 times CoSUB CoSUB IDX1 QX1 R10 QR0 ACC ACC R10 IDX1 R10 R10 QR0 IDX1 IDX1 QX1 Repeat MRW times CoSUB2R CoSUB2R...

Page 172: ...at The major modifications to content are summarized in this table r R In MAC instructions upper case R has replaced lower case r for Reverse operation data4 data5 In MAC instructions immediate shift...

Page 173: ...ags corrected Table 22 Instruction set ordered by Hex code Updated to include section C0 FF MAC instructions and working register indexes Instruction CoMULus Example corrected Table 5 Branch target ad...

Page 174: ...NY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN A SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING ACTIVE IMPLANTED DEVICES OR SYSTEM...

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