STMicroelectronics ST10 Series, Programming Manual

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ST10 FAMILY PROGRAMMING MANUAL
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Note 1. Byte oriented instructions (suffix ‘B’) use Rb instead of Rw (not with [Rw
i
]!).
2.4 - Instruction set ordered by functional
group
The minimum number of state times required for
instruction execution are given for the following
configurations: internal ROM, internal RAM, exter-
nal memory with a 16-bit demultiplexed and multi-
plexed bus or an 8-bit demultiplexed and
multiplexed bus. These state time figures do not
take into account possible wait states on external
busses or possible additional state times induced
by operand fetches. The following notes apply to
this summary:
Data addressing modes
Rw: Word GPR (R0, R1, … , R15).
Rb: Byte GPR (RL0, RH0, …, RL7, RH7).
reg: SFR or GPR (in case of a byte operation
on an SFR, only the low byte can be
accessed via ‘reg’).
mem: Direct word or byte memory location.
[…]: Indirect word or byte memory location.
(Any word GPR can be used as indirect
address pointer, except for the arithmetic,
logical and compare instructions, where
only R0 to R3 are allowed).
bitaddr: Direct bit in the bit-addressable memory
area.
bitoff: Direct word in the bit-addressable mem-
ory area.
#data
x
: Immediate constant (the number of signif-
icant bits that can be user-specified is
given by the appendix “x”).
#mask
8
:Immediate 8-bit mask used for bit-field
modifications.
Multiply and divide operations
The MDL and MDH registers are implicit source
and/or destination operands of the multiply and
divide instructions.
Branch target addressing modes
caddr: Direct 16-bit jump target address
(Updates the Instruction Pointer).
seg: Direct 8-bit segment address (Updates
the Code Segment Pointer).
rel: Signed 8-bit jump target word offset
address relative to the Instruction
Pointer of the following instruction.
#trap7: Immediate 7-bit trap or interrupt number.
Extension operations
The EXT* instructions override the standard DPP
addressing scheme:
#pag: Immediate 10-bit page address.
#seg: Immediate 8-bit segment address.
MOVBS Rw
n
, Rb
m
2 TRAP #trap7 2
MOVBZ reg, mem 4 ATOMIC #data
2
2
mem, reg 4 EXTR
EXTS Rw
m
, #data
2
2 EXTP Rw
m
, #data
2
2
EXTSR #seg, #data
2
4 EXTPR #pag, #data
2
4
NOP - 2 SRST/IDLE - 4
RET PWRDN
RETI SRVWDT
RETS = DISWDT
EINIT
Table 8 : Mnemonic vs address mode & number of bytes (continued)
Mnemonic Addressing Modes Bytes Mnemonic Addressing Modes Bytes