L6482
Pin connection
Doc ID 023768 Rev 1
17/73
36
HVGA2
Power output
High-side half bridge A2 gate driver output
17
HVGB1
Power output
High-side half bridge B1 gate driver output
22
HVGB2
Power output
High-side half bridge B2 gate driver output
1
LVGA1
Power output
Low-side half bridge A1 gate driver output
38
LVGA2
Power output
Low-side half bridge A2 gate driver output
19
LVGB1
Power output
Low-side half bridge B1 gate driver output
20
LVGB2
Power output
Low-side half bridge B2 gate driver output
8
PGND
Ground
Power ground pins. They must be connected to other
ground pins
35
SENSEA
Analog input
Phase A current sensing input
23
SENSEB
Analog input
Phase B current sensing input
2
OUTA1
Power input
Full bridge A output 1
37
OUTA2
Power input
Full bridge A output 2
18
OUTB1
Power input
Full bridge B output 1
21
OUTB2
Power input
Full bridge B output 2
16
AGND
Ground
Analog ground. It must be connected to other ground
pins
33
SW
Logical input
External switch input pin
29
DGND
Ground
Digital ground. It must be connected to other ground
pins
28
SDO
Logical output
Data output pin for serial interface
26
SDI
Logical input
Data input pin for serial interface
25
CK
Logical input
Serial interface clock
24
CS
Logical input
Chip select input pin for serial interface
30
BUSY/SYNC Open drain output
By default, the BUSY / SYNC pin is forced low when
the device is performing a command.
The pin can be programmed in order to generate a
synchronization signal
31
FLAG
Open drain output
Status flag pin. An internal open drain transistor can
pull the pin to GND when a programmed alarm
condition occurs (step loss, OCD, thermal pre-warning
or shutdown, UVLO, wrong command, non-
performable command)
34
STBY
RESET
Logical input
Standby and reset pin. LOW logic level puts the device
in Standby mode and reset logic.
If not used, it should be connected to V
REG
32
STCK
Logical input
Step-clock input
EPAD
Exposed pad Ground
Exposed pad. It must be connected to other ground
pins
Table 6.
Pin description (continued)
No.
Name
Type
Function
