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This is information on a product in full production.

October 2012

Doc ID 023768 Rev 1

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L6482

Fully integrated microstepping motor driver

with motion engine and SPI

Datasheet

−

production data

Features

■

Operating voltage: 7.5 V - 85 V

■

Dual full bridge gate driver for N-channel
MOSFETs

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Fully programmable gate driving

■

Embedded Miller clamp function

■

Programmable speed profile

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Up to 1/16 microstepping

■

Advanced current control with auto-adaptive
decay mode

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Integrated voltage regulators

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SPI interface

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Low quiescent standby currents

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Programmable non-dissipative overcurrent
protection

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Overtemperature protection

Applications

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Bipolar stepper motor

Description

The L6482, realized in analog mixed signal
technology, is an advanced fully integrated
solution suitable for driving two-phase bipolar
stepper motors with microstepping.

It integrates a dual full bridge gate driver for N-
channel MOSFET power stages with embedded

non-dissipative overcurrent protection. Thanks to
a new current control, a 1/16 microstepping is
achieved through an adaptive decay mode which
outperforms traditional implementations. The
digital control core can generate user defined
motion profiles with acceleration, deceleration,
speed or target position easily programmed
through a dedicated register set. All application
commands and data registers, including those
used to set analog values (i.e. current protection
trip point, deadtime, PWM frequency, etc.) are
sent through a standard 5-Mbit/s SPI. A very rich
set of protections (thermal, low bus voltage,
overcurrent and motor stall) make the L6482
“bullet proof”, as required by the most demanding
motor control applications.

HTSSOP38

Table 1.

Device summary

Order code

Package

Packaging

L6482H

HTSSOP38

Tube

L6482HTR

HTSSOP38

Tape and reel

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2
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Summary of Contents for HTSSOP38

Page 1: ...ase bipolar stepper motors with microstepping It integrates a dual full bridge gate driver for N channel MOSFET power stages with embedded non dissipative overcurrent protection Thanks to a new current control a 1 16 microstepping is achieved through an adaptive decay mode which outperforms traditional implementations The digital control core can generate user defined motion profiles with accelera...

Page 2: ...Logic I O 19 6 3 Charge pump 19 6 4 Microstepping 20 6 4 1 Automatic Full step and Boost modes 21 6 5 Absolute position counter 22 6 6 Programmable speed profiles 22 6 6 1 Infinite acceleration deceleration mode 22 6 7 Motor control commands 23 6 7 1 Constant speed commands 23 6 7 2 Positioning commands 23 6 7 3 Motion commands 24 6 7 4 Stop commands 25 6 7 5 Step clock mode 25 6 7 6 GoUntil and R...

Page 3: ...internal voltage regulators 33 6 19 BUSY SYNC pin 34 6 20 FLAG pin 34 7 Phase current control 35 7 1 Predictive current control 35 7 2 Auto adjusted decay mode 36 7 3 Auto adjusted fast decay during the falling steps 38 7 4 Torque regulation output current amplitude regulation 39 8 Serial interface 41 9 Programming manual 43 9 1 Register and flag description 43 9 1 1 ABS_POS 44 9 1 2 EL_POS 44 9 1...

Page 4: ...2 2 Nop 62 9 2 3 SetParam PARAM VALUE 62 9 2 4 GetParam PARAM 62 9 2 5 Run DIR SPD 63 9 2 6 StepClock DIR 63 9 2 7 Move DIR N_STEP 64 9 2 8 GoTo ABS_POS 64 9 2 9 GoTo_DIR DIR ABS_POS 65 9 2 10 GoUntil ACT DIR SPD 65 9 2 11 ReleaseSW ACT DIR 66 9 2 12 GoHome 66 9 2 13 GoMark 66 9 2 14 ResetPos 67 9 2 15 ResetDevice 67 9 2 16 SoftStop 67 9 2 17 HardStop 68 9 2 18 SoftHiZ 68 9 2 19 HardHiZ 68 9 2 20 ...

Page 5: ...e 50 Table 21 Overcurrent detection threshold 50 Table 22 STEP_MODE register 51 Table 23 Step mode selection 51 Table 24 SYNC output frequency 52 Table 25 SYNC signal source 52 Table 26 ALARM_EN register 52 Table 27 GATECFG1 register 53 Table 28 IGATE parameter 53 Table 29 TCC parameter 54 Table 30 TBOOST parameter 54 Table 31 GATECFG2 register voltage mode 54 Table 32 TDT parameter 55 Table 33 TB...

Page 6: ... 65 Table 56 GoUntil command structure 65 Table 57 ReleaseSW command structure 66 Table 58 GoHome command structure 66 Table 59 GoMark command structure 66 Table 60 ResetPos command structure 67 Table 61 ResetDevice command structure 67 Table 62 SoftStop command structure 67 Table 63 HardStop command structure 68 Table 64 SoftHiZ command structure 68 Table 65 HardHiZ command structure 68 Table 66 ...

Page 7: ...pin configuration 27 Figure 13 Overcurrent detection principle scheme 28 Figure 14 External switch connection 31 Figure 15 Gate driving currents 32 Figure 16 Device supply pin management 33 Figure 17 Predictive current control 35 Figure 18 Non predictive current control 36 Figure 19 Adaptive decay fast decay tuning 37 Figure 20 Adaptive decay switch from normal to slow fast decay mode and vice ver...

Page 8: ...CK SDO SDI BUSY SYNC SW STCK DGND VDD ADCIN VCC CP VBOOT PGND VS CORE LOGIC VCC HVGA1 LVGA1 HVGA2 LVGA2 HVB1 LVGB1 OUTA1 OUTA2 OUTB1 HVGB2 LVGB2 OUTB2 Vboot Vboot Vboot Vboot VSENSEA VSENSEB AGND VCC VCC VCC Voltage reg VCC VSREG VCC REG Ext Osc driver Clock gen OSCIN OSCOUT 16 MHz Oscillator Temperature sensing VREG Voltage reg VREG AM15031v1 ...

Page 9: ... VREG regulator supply voltage 18 V VOUT1A VOUT2A VOUT1B VOUT2B Full bridge output voltage DC 5 to VBOOT V AC 15 to VBOOT SRout Full bridge output slew rate 10 90 10 V ns VHVG1A VHVG2A VHVG1B VHVG2B High side output driver voltage VOUT to VBOOT V ΔVHVG1A ΔVHVG2A ΔVHVG1B ΔVHVG2B High side output driver to respective bridge output voltage VHVG VOUT 15 V VLVG1A VLVG2A VLVG1B VLVG2B Low side output dr...

Page 10: ... Typ Max Unit VDD Logic interface supply voltage 3 3 V logic outputs 3 3 V 5 V logic outputs 5 VREG Logic supply voltage 3 3 V VS Motor supply voltage VSREG 85 V VSREG Internal VCC voltage regulator VCC voltage internally generated VCC 3 Vs V VCC Gate driver supply voltage VCC voltage imposed by external source VSREG VCC 7 5 15 V VCCREG Internal VREG voltage regulator supply voltage VREG voltage i...

Page 11: ...hold 1 2 8 3 3 18 V VREGthOff VREG turn off threshold 1 2 2 2 4 2 5 V IVSREGqu Undervoltage VSREG quiescent supply current VCCREG VREG 2 2 V 40 μA IVSREGq Quiescent VSREG supply current VCCREG VREG 3 3 V internal oscillator selected 1 3 8 mA IVSREGq Quiescent VSREG supply current VCCREG VREG 15V 6 5 mA Thermal protection Tj WRN Set Thermal warning temperature 135 C Tj WRN Rec Thermal warning recov...

Page 12: ... 77 82 96 112 IOB High side and low side turn off overboost gate current 85 103 117 mA RCLAMP LS Low side gate driver Miller clamp resistance 6 5 10 Ω RCLAMP HS High side gate driver Miller clamp resistance 3 10 Ω VGATE CLAMP High side gate voltage clamp IGATE CLAMP 100 mA 16 7 v tcc Programmable constant gate current time 2 TCC 00000 125 ns TCC 11111 3750 tOB Programmable Turn off overboost gate ...

Page 13: ...pull up resistor 430 kΩ RPDRST STBY RESET pull down resistor 450 RPUSW SW pull up resistor 80 thigh STCK Step clock input high time 300 ns tlow STCK Step clock input low time 300 ns Internal oscillator and external oscillator driver fosc int Internal oscillator frequency Tj 25 C 5 16 5 MHz fosc ext Programmable external oscillator frequency 8 32 MHz VOSCOUTH OSCOUT clock source high level voltage ...

Page 14: ... 1000 mV VREF min Minimum reference voltage 7 8 mV Overcurrent protection VOCD Programmable overcurrent detection voltage VDS threshold OCD_TH 11111 800 1000 1100 mV OCD_TH 00000 27 31 35 mV OCD_TH 01001 270 312 5 344 mV OCD_TH 10011 500 625 688 mV tOCD Comp OCD comparator delay 100 200 ns tOCD Flag OCD to flag signal delay time 230 530 ns tOCD SD OCD to shutdown delay time OCD_TH 11111 OCD event ...

Page 15: ...tage regulator output current VREG pin shorted to ground 125 mA IREGOUT STB Y Internal VREG voltage regulator output standby current VREG pin shorted to ground 55 mA PREG Internal VREG voltage regulator power dissipation 0 5 W Integrated analog to digital converter NADC Analog to digital converter resolution 5 bit VADC ref Analog to digital converter reference voltage 3 3 V fS Analog to digital co...

Page 16: ... 13 VREG Power supply Logic supply voltage 27 VDD Power supply Logic interface supply voltage 12 VSREG Power supply Internal VCC voltage regulator supply voltage 10 VCC Power supply Gate driver supply voltage 14 OSCIN Analog input Oscillator pin1 To connect an external oscillator or clock source 15 OSCOUT Analog output Oscillator pin2 To connect an external oscillator When the internal oscillator ...

Page 17: ...ed to other ground pins 33 SW Logical input External switch input pin 29 DGND Ground Digital ground It must be connected to other ground pins 28 SDO Logical output Data output pin for serial interface 26 SDI Logical input Data input pin for serial interface 25 CK Logical input Serial interface clock 24 CS Logical input Chip select input pin for serial interface 30 BUSY SYNC Open drain output By de...

Page 18: ...0 nF D1 Charge pump diodes Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 STD25NF10 RPU 39 kΩ RSENSE 0 2 Ω maximum phase current 5 A CK SDO SDI SW STCK DGND VDD ADCIN Analog signal VCC CP VBOOT PGND VS STBY RESET FLAG CS BUSY SYNC HVGA1 L VGA1 LVGA2 HVGA2 HVGB1 LVGB1 OUTA1 OUTA2 OUTB1 LVGB2 HVGB2 SENSEB OUTB2 SENSEA AGND VSREG VCCREG OSCIN OSCOUT VREG L6482 CFL Y C V S CVCC C VCCREG CVDD CVSREG CBOOT C VSPOL VS C VREG C...

Page 19: ...ogicwu must pass before applying a command to allow proper oscillator and logic startup Any movement command makes the device exit from High Z state HardStop and SoftStop included 6 2 Logic I O Pins CS CK SDI STCK SW and STBY RESET are TTL CMOS 3 3 V 5 V compatible logic inputs Pin SDO is a TTL CMOS compatible logic output VDD pin voltage imposes a logical output voltage range Pins FLAG and BUSY S...

Page 20: ... microstepping sinewave that is generated is reset to the first microstep and the absolute position counter value Section 6 5 becomes meaningless Figure 5 Normal mode and microstepping 16 microsteps VS VS V CP D1 D2 VCP fPUMP to high side gate drivers VS V CP V D1 CBOOT CFLY D1 D2 VBOOT CP VDD V V Charge pump oscillator AM15034v1 step 1 step 1 step 2 step 3 step 4 step 1 Reset position step 1 step...

Page 21: ...through the related parameter in the FS_SPD register Section 9 1 9 When the BOOST_MODE bit of the FS_SPD register is low default the amplitude of the voltage squarewave in Full step mode is equal to the peak of the voltage sinewave multiplied by sine π 4 Figure 6 This avoids the current drop between the two driving modes When the BOOST_MODE bit of the FS_SPD register is high the amplitude of the v...

Page 22: ...le that performs a motor motion compliant to speed profile boundaries All acceleration parameters are expressed in step tick2 and all speed parameters are expressed in step tick the unit of measurement does not depend on the selected step mode Acceleration and deceleration parameters range from 2 40 to 212 2 2 40 step tick2 equivalent to 14 55 to 59590 step s2 Minimum speed parameter ranges from 0...

Page 23: ... user defined target speed starting from the programmed minimum speed set in the MIN_SPEED register and with the programmed acceleration deceleration value set in the ACC and DEC registers A new constant speed command can be requested anytime Figure 9 Constant speed command examples 6 7 2 Positioning commands An absolute positioning command produces a motion in order to reach a user defined positi...

Page 24: ...Figure 11 Performed motor motion is compliant to programmed speed profile boundaries acceleration deceleration minimum and maximum speed Note that with some speed profiles or motion commands the deceleration phase can start before the maximum speed is reached Figure 11 Motion command examples AM15040v1 Forward direction 0 221 221 1 0 221 221 1 Present position Target position Present position Targ...

Page 25: ...f the STCK signal frequency the MOT_STATUS parameter in the STATUS register equal to 00 6 7 6 GoUntil and ReleaseSW commands In most applications the power up position of the stepper motor is undefined so an initialization algorithm driving the motor to a known position is necessary The GoUntil and ReleaseSW commands can be used in combination with external switch input see Section 6 14 to easily ...

Page 26: ...ected crystal ceramic resonator or direct clock source Four programmable clock frequencies are available for each external clock source 8 16 24 and 32 MHz When an external crystal resonator is selected the OSCIN and OSCOUT pins are used to drive the crystal resonator see Figure 12 The crystal resonator and load capacitors CL must be placed as close as possible to the pins Refer to Table 8 for the ...

Page 27: ...ogrammed threshold the OCD flag in the STATUS register is forced low until the event expires and a GetStatus command is sent to the device Section 9 1 21 and Section 9 2 20 The overcurrent event expires when all the Power MOSFET VDS voltages fall below the programmed threshold The overcurrent threshold can be programmed by the OCD_TH register in one of 32 available values ranging from 31 25 mV to ...

Page 28: ... GetStatus command 6 10 Undervoltage lockout UVLO The L6482 provides a programmable gate driver supply voltage UVLO protection When one of the supply voltages of the gate driver VCC for the low sides and VBOOT VS for the high sides falls below the respective turn off threshold an undervoltage event occurs In this case all gates are immediately turned off and the UVLO flag in the STATUS register is...

Page 29: ...ing condition and it expires when the temperature falls below the Tj WRN Rel threshold When the Tj OFF Set threshold is reached all the gates are turned off and the gate driving circuitry is disabled Miller clamps are still operative This condition expires when the temperature falls below the Tj OFF Rel threshold When the Tj SD OFF threshold is reached all the gates are turned off using Miller cla...

Page 30: ... Section 9 2 15 6 14 External switch SW pin The SW input is internally pulled up to VDD and detects if the pin is open or connected to ground see Figure 14 The SW_F bit of the STATUS register indicates if the switch is open 0 or closed 1 Section 9 1 21 the bit value is refreshed at every system clock cycle 125 ns The SW_EVN flag of the STATUS register is raised when a switch turn on event SW input...

Page 31: ...ent for all the controlled current time period At the end of the controlled current phase the gate of the external MOSFET should be completely charged otherwise the gate driving circuitry continues to charge it using a holding current This current is equal to IGATE for the low side gate drivers and 1 mA for the high side ones During turn off the gate driver discharges the gate sinking an IGATE cur...

Page 32: ...can be programmed within a range from 125 ns to 4 μs with a resolution of 125 ns TDT parameter in the GATECFG2 register see Section 9 1 19 At the end of each commutation the overcurrent and stall detection comparators are disabled blanking in order to avoid the respective systems detecting body diode turn off current peaks The duration of blanking time is programmable through the TBLANK parameter ...

Page 33: ...ent If VCC is externally supplied the VSREG and VCC pins must be shorted VSREG must be compliant with VCC range If VREG is externally supplied the VCCREG and VREG pins must be shorted and equal to 3 3 V VSREG must be always less than VBOOT in order to avoid related ESD protection diode turn on The device can be protected from this event by adding an external low drop diode between the VSREG and VS...

Page 34: ...ccurs Power up or standby reset exit Overcurrent detection Thermal warning Thermal shutdown UVLO UVLO on ADC input Switch turn on event Command error It is possible to mask one or more alarm conditions by programming the ALARM_EN register see Section 9 1 17 Table 26 If the corresponding bit of the ALARM_EN register is low the alarm condition is masked and it does not cause a FLAG pin transition al...

Page 35: ...n independent control system that shares with the other bridge the control parameters only 7 1 Predictive current control Unlike classical peak current control systems that make the phase current decay when the target value is reached this new method keeps the power bridge ON for an extra time after reaching the current threshold At each cycle the system measures the time required to reach the tar...

Page 36: ...F state as shown in Figure 18 Figure 18 Non predictive current control 7 2 Auto adjusted decay mode During the current control the device automatically selects the better decay mode in order to follow the current profile reducing the current ripple At reset the off time is performed turning on both the low side MOS of the power stage and the current recirculates in the lower half of the bridge slo...

Page 37: ...current threshold is increased by a microstep change rising step the system returns to normal decay mode slow decay only and the tFAST value is halved Stopping the motor or reaching the current sinewave zero crossing causes the current control system to return to the reset state reference current 1st fast decay Tfast TOFF_FAST 8 2nd fast decay Tfast TOFF_FAST 4 Note starting from 2nd fast decay th...

Page 38: ...y time within the same falling step an extra fast decay is necessary to obtain an on time greater than TON_MIN see Section 9 1 12 The maximum tFALL value is equal to FALL_STEP At the next falling step the system uses the last tFALL value of the previous falling step Stopping the motor or reaching the current sinewave zero crossing causes the current control system to return to the reset state Figu...

Page 39: ...ce voltage can be regulated in two ways writing TVAL_ACC TVAL_DEC TVAL_RUN and TVAL_HOLD registers or varying the ADCIN voltage value The EN_TQREG bit CONFIG register sets the torque regulation method If this bit is high ADC_OUT prevalue is used to regulate output current amplitude see Table 20 Section 9 1 14 Otherwise the internal analog to digital converter is at the user s disposal and the outp...

Page 40: ...Rev 1 Figure 22 Current sensing and reference voltage generation Load Rsense To gate drivers To current control logic Peak reference DAC TVAL_X or ADCIN Microstep Microstepping DAC To gate drivers To gate drivers To gate drivers SENSEX Vref AM15047v1 ...

Page 41: ... bit first The SDI is sampled on the rising edges of the CK All output data bytes are shifted out of the device through the SDO output most significant bit first The SDO is latched on the falling edges of the CK When a return value from the device is not available an all zero byte is sent After each byte transmission the CS input must be raised and be kept high for at least tdisCS in order to allo...

Page 42: ...D 023768 Rev 1 Figure 24 Daisy chain configuration AM15054v1 HOST HOST SPI signals DEV 1 CS SDO M SDI M CS CK SDI SDO CS CK SDI M SDO M DEV 2 CS CK SDI SDO DEV N CS CK SDI SDO Byte N Byte N Byte N Byte N Byte N 1 Byte N 1 Byte 1 Byte 1 ...

Page 43: ... MAX_SPEED Maximum speed 10 041 248e 6 step tick 991 8 step s R WR h08 MIN_SPEED Minimum speed 12 000 0 step tick 0 step s R WS h15 FS_SPD Full step speed 10 027 150 7e 6 step tick 602 7 step s R WR h09 TVAL_HOLD Holding reference voltage 7 29 328 mV R WR h0A TVAL_RUN Constant speed reference voltage 7 29 328 mV R WR h0B TVAL_ACC Acceleration starting reference voltage 7 29 328 mV R WR h0C TVAL_DE...

Page 44: ...e new electrical position is instantly imposed When the EL_POS register is written its value must be masked in order to match h18 GATECFG1 Gate driver configuration 11 0 Igate 4 mA tCC 125 ns no boost R WH h19 GATECFG2 Gate driver configuration 8 0 tBLANK 125 ns tDT 125 ns R WH h1A CONFIG IC configuration 16 2C88 Internal 16 MHz oscillator OSCOUT 2 MHz SW event causes HardStop motor supply voltage...

Page 45: ...d Equation 1 where SPEED is the integer number stored in the register and tick is 250 ns The available range is from 0 to 15625 step s with a resolution of 0 015 step s Note The range effectively available to the user is limited by the MAX_SPEED parameter Any attempt to write the register causes the command to be ignored and the NOTPERF_CMD flag to rise Section 9 1 21 9 1 5 ACC The ACC register co...

Page 46: ...ister contains the speed profile maximum speed expressed in step tick format unsigned fixed point 0 18 In order to convert it in step s the following formula can be used Equation 4 where MAX_SPEED is the integer number stored in the register and tick is 250 ns The available range is from 15 25 to 15610 step s with a resolution of 15 25 step s 9 1 8 MIN_SPEED The MIN_SPEED register contains the fol...

Page 47: ...alent to a speed threshold of about 7 63 step s The available range is from 7 63 to 15625 step s with a resolution of 15 25 step s The BOOST_MODE bit sets the amplitude of the voltage squarewave during the full step operation see Section 6 4 1 9 1 10 TVAL_HOLD TVAL_RUN TVAL_ACC and TVAL_DEC The TVAL_HOLD register contains the current value that is assigned to the torque regulation DAC when the mot...

Page 48: ... is used by the current control system when current mode operation is selected The TON_MIN register contains the minimum on time value used by the current control system see Section 7 2 The available range for both parameters is from 0 5 µs to 64 µs Table 15 Torque regulation by TVAL_HOLD TVAL_ACC TVAL_DEC and TVAL_RUN registers TVAL_X 6 0 Output current amplitude 0 0 0 0 0 0 0 7 8 mV 0 0 0 0 0 0 ...

Page 49: ... minimum off time value used by the current control system see Section 7 1 for details The available range for both parameters is from 0 5 µs to 64 µs Any attempt to write to the register when the motor is running causes the command to be ignored and NOTPERF_CMD to rise see Section 9 1 21 Table 18 Minimum on time TON MIN 6 0 Time 0 0 0 0 0 0 0 0 5 µs 0 0 0 0 0 0 1 1 µs 1 1 1 1 1 1 0 63 5 µs 1 1 1 ...

Page 50: ...The OCD_TH register contains the overcurrent threshold value see Section 6 9 for details The available range is from 375 mA to 6 A steps of 375 mA as shown in Table 21 Table 20 ADC_OUT value and torque regulation feature VADCIN VREG ADC_OUT 4 0 Reference voltage 0 0 0 0 0 0 31 25 mV 1 32 0 0 0 0 1 62 5 mV 30 32 1 1 1 1 0 968 8 mV 31 32 1 1 1 1 1 1 V Table 21 Overcurrent detection threshold OCD_TH ...

Page 51: ... write the register when the motor is running causes the command to be ignored and the NOTPERF_CMD flag to rise see Section 9 1 21 When the SYNC_EN bit is set low the BUSY SYNC output is forced low during the command execution otherwise when the SYNC_EN bit is set high the BUSY SYNC output provides a clock signal according to the SYNC_SEL parameter Table 22 STEP_MODE register Bit 7 Bit 6 Bit 5 Bit...

Page 52: ...frequency 000 001 010 011 100 101 110 111 SYNC_SEL 000 fFS 2 fFS 2 fFS 2 fFS 2 fFS 2 fFS 2 fFS 2 fFS 2 001 NA fFS fFS fFS fFS fFS fFS fFS 010 NA NA 2 fFS 2 fFS 2 fFS 2 fFS 2 fFS 2 fFS 011 NA NA NA 4 fFS 4 fFS 4 fFS 4 fFS 4 fFS 100 NA NA NA NA 8 fFS 8 fFS 8 fFS 8 fFS 101 NA NA NA NA NA NA NA NA 110 NA NA NA NA NA NA NA NA 111 NA NA NA NA NA NA NA NA Table 25 SYNC signal source SYNC_SEL 2 0 Source 0...

Page 53: ...The TCC parameter defines the duration of constant current phase during gate turn on and turn off sequences Section 6 15 2 Thermal warning 3 UVLO 4 ADC UVLO 5 Unused 6 Switch turn on event 7 MSB Command error Table 26 ALARM_EN register continued ALARM_EN bit Alarm condition Table 27 GATECFG1 register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 WD_EN TBOOST Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B...

Page 54: ...parameter TCC 4 0 Constant current time ns 0 0 0 0 0 125 0 0 0 0 1 250 1 1 1 0 0 3625 1 1 1 0 1 3750 1 1 1 1 0 3750 1 1 1 1 1 3750 Table 30 TBOOST parameter TBOOST Turn off boost time 2 0 ns 0 0 0 0 0 0 1 62 5 1 83 3 2 125 3 1 Clock frequency equal to 16 MHz or 32 MHz 2 Clock frequency equal to 24 MHz 3 Clock frequency equal to 8 MHz 0 1 0 125 0 1 1 250 1 0 0 375 1 0 1 500 1 1 0 750 1 1 1 1000 Tab...

Page 55: ...ection 6 16 9 1 20 CONFIG The CONFIG register has the following structure The OSC_SEL and EXT_CLK bits set the system clock source Table 32 TDT parameter TDT 4 0 Deadtime ns 0 0 0 0 0 125 0 0 0 0 1 250 1 1 1 1 0 3875 1 1 1 1 1 4000 Table 33 TBLANK parameters TBLANK 2 0 Blanking time ns 0 0 0 125 0 0 1 250 1 1 0 875 1 1 1 1000 Table 34 CONFIG register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9...

Page 56: ... 0 1 0 1 External crystal or resonator 16 MHz Crystal resonator driving Crystal resonator driving 0 1 1 0 External crystal or resonator 24 MHz Crystal resonator driving Crystal resonator driving 0 1 1 1 External crystal or resonator 32 MHz Crystal resonator driving Crystal resonator driving 1 1 0 0 Ext clock source 8 MHz crystal resonator driver disabled Clock source Supplies inverted OSCIN signal...

Page 57: ...r the TVAL_HOLD TVAL_ACC TVAL_DEC and TVAL_RUN registers internal The TSW parameter is used by the current control system and it sets the target switching period Table 37 Overcurrent event OC_SD Overcurrent event 1 Bridges shutdown 0 Bridges do not shutdown VCCVAL VCC voltage 0 7 5 V 1 15 V Table 39 Programmable UVLO thresholds UVLOVAL VCCthOn VCCthOff ΔVBOOTthOn ΔVBOOTthOff 0 6 9 V 6 3 V 6 V 5 5 ...

Page 58: ...flag is active low and is set by an undervoltage lockout or reset events power up included The UVLO_ADC flag is active low and indicates an ADC undervoltage event The OCD flag is active low and indicates an overcurrent detection event The CMD_ERROR flag is active high and indicates that the command received by SPI can t be performed or does not exist at all The SW_F reports the SW input status low...

Page 59: ...d The STCK_MOD bit is an active high flag indicating that the device is working in Step clock mode In this case the step clock signal should be provided through the STCK input pin The DIR bit indicates the current motor direction MOT_STATUS indicates the current motor status Any attempt to write to the register causes the command to be ignored and the NOTPERF_CMD to rise Section 9 1 21 Table 44 ST...

Page 60: ...direction GoUntil ACT DIR SPD 100 0 ACT 01 DIR Performs a motion in DIR direction with speed SPD until SW is closed the ACT action is executed then a SoftStop takes place ReleseSW ACT DIR 100 1 ACT 01 DIR Performs a motion in DIR direction at minimum speed until the SW is released open the ACT action is executed then a HardStop takes place GoHome 011 1 0 00 0 Brings the motor in HOME position GoMa...

Page 61: ...commands can be sent If a command requiring a response is sent before the previous response is completed the response transmission is aborted and the new response is loaded into the output communication buffer see Figure 27 Figure 27 Command response aborted When a byte that does not correspond to a command is sent to the IC it is ignored and the WRONG_CMD flag in the STATUS register is raised see...

Page 62: ... particular conditions see Table 11 any attempt to write one of those registers when the conditions are not satisfied causes the command to be ignored and the NOTPERF_CMD flag to rise at the end of the last argument byte see Section 9 1 21 Any attempt to set an inexistent register wrong address value causes the command to be ignored and the WRONG_CMD flag to rise at the end of the command byte as ...

Page 63: ...gned fixed point 0 28 that is the same format as the SPEED register Section 9 1 4 Note The SPD value should be lower than MAX_SPEED and greater than MIN_SPEED otherwise the Run command is executed at MAX_SPEED or MIN_SPEED respectively This command keeps the BUSY flag low until the target speed is reached This command can be given anytime and is immediately executed 9 2 6 StepClock DIR The StepClo...

Page 64: ...ode full half quarter etc This command keeps the BUSY flag low until the target number of steps is performed This command can only be performed when the motor is stopped If a motion is in progress the motor must be stopped and it is then possible to perform a move command Any attempt to perform a move command when the motor is running causes the command to be ignored and the NOTPERF_CMD flag to ri...

Page 65: ...n BUSY low causes the command to be ignored and the NOTPERF_CMD flag to rise Section 9 1 21 9 2 10 GoUntil ACT DIR SPD The GoUntil command produces a motion at SPD speed imposing a forward DIR 1 or a reverse DIR 0 direction When an external switch turn on event occurs Section 6 14 the ABS_POS register is reset if ACT 0 or the ABS_POS register value is copied into the MARK register if ACT 1 the sys...

Page 66: ... the motion is performed at 5 step s The ReleaseSW command keeps the BUSY flag low until the switch input is released and the motor is stopped 9 2 12 GoHome The GoHome command produces a motion to the HOME position zero position via the shortest path Note that this command is equivalent to the GoTo 0 0 command If a motor direction is mandatory the GoTo_DIR command must be used Section 9 2 9 The Go...

Page 67: ...er to zero The zero position is also defined as the HOME position Section 6 5 9 2 15 ResetDevice The ResetDevice command resets the device to power up conditions Section 6 1 Note At power up the power bridges are disabled 9 2 16 SoftStop The SoftStop command causes an immediate deceleration to zero speed and a consequent motor stop the deceleration value used is the one stored in the DEC register ...

Page 68: ...bridges are disabled the HiZ flag is raised When the motor is stopped a SoftHiZ command forces the bridges to enter high impedance state This command can be given anytime and is immediately executed This command keeps the BUSY flag low until the motor is stopped 9 2 19 HardHiZ The HardHiZ command immediately disables the power bridges high impedance state and raises the HiZ flag When the motor is ...

Page 69: ...The GetStatus command resets the STATUS register warning flags The command forces the system to exit from any error state The GetStatus command DOES NOT reset the HiZ flag Table 66 GetStatus command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 0 1 0 0 0 0 from host STATUS MSByte to host STATUS LSByte to host ...

Page 70: ...l of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Figure 28 HTSSOP38 package dimensions Table 67 HTSSOP38 mechanical data Symbol mm Min Typ Max A 1 1 A1 0 05 0 15 A2 0 85 0 9 0 95 b 0 17 0 27 c 0 09 0 20 D 9 60 9 70 9 80 E1 4 30 4 40 4 50 e 0 50 E 6 40 L 0 50 0 60 0 70 P 6 40 6 50 6 60 P1 3 10 3 20 3 30 ...

Page 71: ...L6482 Package mechanical data Doc ID 023768 Rev 1 71 73 Figure 29 HTSSOP38 footprint ...

Page 72: ...Revision history L6482 72 73 Doc ID 023768 Rev 1 11 Revision history Table 68 Document revision history Date Revision Changes 08 Oct 2012 1 Initial release ...

Page 73: ...ARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICA...

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