Hardware Reference Guide
SST-PFB3-PCI
3.1 PFB3-PCI Card Configuration Registers
This section provides hardware register details for the SST-PFB3-PCI card.
3.1.1 Host Register Layout
The SST-PFB3-PCI host registers are mapped into a separate region of PCI memory space (PCI Region 3). The base
mapping address in the host system can be found by reading the PCI configuration space at offset 0x1C. Refer to
Section 3.2,
SST-PFB3-PCI Configuration Space
, for PCI configuration space information.
Note
When power is applied to the card, or after a physical reset from the system,
it may take up to 2 seconds for the card to initialize. Successful initialization can be
confirmed by monitoring the LEDs or by reading the HDR register, as described in
Section C.1.1,
Verify Card Presence
.
Table 4: Host Register Layout
The following table maps the host register layout.
Offset
Register
Bit Name
Name
7
6
5
4
3
2
1
0
00h Control CardRun
MemEn IntEn WdTout
HostIrq1
HostIrq0
CardIrq1
CardIrq0
01h
AddrMatch 1 AM18 AM17 AM16 AM15 AM14
Reserved
Reserved
02h
BankAddress
0 0 0
BA16
BA15
BA14
Reserved
Reserved
03h WinSize WS19 WS18 WS17 WS16 WS15 WS14 WS13 WS12
04h HostIrq Reserved
Reserved
Reserved Reserved
IrqLevel
05h
LedReg Reserved Reserved Reserved Reserved CommRed CommGrn SYSRed SYSGrn
06h
HWReset Reserved Reserved JTAGEN CPUTRST
CPUTMS CPUTDI CPUTCK
07h
HDR
HostDataReg (written by CPU)
08h-
01Fh
Reserved
24
Hardware Register Details
©2003 Woodhead Software and Electronics, a division of Woodhead Canada Limited.
Document Edition: 1.0, Document #: 715-0060, Template Edition: 1.0, Template #: QMS-06-045.
Use, duplication or disclosure of this document or any of the information contained herein is subject to the restrictions on page ii of this document.
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