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Five 74HC374 Octal Flip-Flops provide latched output bits, and two
74HC244 Octal Buffers provide input bits to the buffered data bus. The
front panel switch connector J301 provides eight outputs for the LED's
on the front panel, along with +5 V power and ground. Eight input lines
are also provided to read the status of the front panel keypad switches.
Dual D-Type Flip-flops U307, 312, and 313 are used to store interrupt
requests from the gated integrator RAM circuit. The processor can
then identify the source of an interrupt through U303.
Jumpers J301 and J302 are used to select the type of oscillator that is
installed in the receiver.
Gated Integrators (p. 5/14)
There are four gated integrators used to integrate the incoming LORAN
signal. All of the integrators are basically the same, so the following
description will refer to components in the first integrator. Capacitor
C401 integrates the output of U401A, an LM13600 Operational
Transconductance Amplifier(OTA). The input to the OTA is the LORAN
signal. The output of the OTA is turned on only when U410A is turned
on by a -GATE1 signal. In this manner, integration of the LORAN
signal occurs only during the time the gate is active, which allows
integrating over any specified interval on the LORAN pulse. To
discharge the integrating capacitor, switch U403A is kept closed until
just before a gate occurs. The charge on the integrating capacitor is
buffered to the analog-to-digital converter multiplexer by U402. The
amplifier is configured for unity gain, but resistor divider R403 and
R404 limits the maximum output level fed to the A/D converter.
Because the phase of specific LORAN pulses changes, U51 allows the
inputs to the last three integrators to be switched between the inverting
and non-inverting OTA inputs, thus ensuring that the sign of the
integrator outputs can be controlled. The last two integrators also have
a provision for integrating over a ten-times longer interval by having
larger integrating capacitors C405 and C406 switched onto the OTA
output by switches U409A and U409B.
Gated Integrator Pattern Ram (p. 6/14)
The GATE, CARRIER, and CLEAR lines for the gated integrators are
generated by clocking through a pattern stored in U506, an 8 kilobyte
static RAM. The processor loads the memory locations through U510,
an Octal Bus Transceiver, and the integrators are driven through U509,
an Octal D-Type Flip-Flop. U508 is a multiplexer that generates the
required control logic for writing and reading. U503 through U505 and
U507B form a 13-bit counter that counts up from 3192 decimal,
selecting the top 5000 RAM addresses. At the 200 ns period of the 5
MHz clock, this gives a 1 ms repeat time, which is the separation
between LORAN pulses. The multiplexer U508 selects -GATE _CS as
