45
Integrator Tests
The integrators may be tested by applying a 100 kHz test signal to the
antenna input through the ANTENNA TERMINATOR as described
above. Set the attenuators (in CAL MENU 1) to 64 dB and adjust the
signal level to get about 6 V pk-pk at the LORAN OUTPUT.
The integrator gate type and position may be controlled in CAL MENU
1. The first screen allows setting the gate types to either NORM,
CAL1, or CAL2. CAL1 and CAL2 are the test settings. The CAL 1
setting tests the high gain settings of the integrators. CAL 2 tests the
high gain setting of integrators 1 and 2 and the low gain setting of
integrators 3 and 4. The second screen allows the gate position to be
changed and displays the integrator output data. The gate position
may be set to any value between 75 and 4500. Each step corresponds
to a 200 ns difference in position (50 steps = 10
µ
s = 1 cycle of input).
The integrator output data has an ADC range of -128 to +127
corresponding to -5V to +5V.
In either gate position, stepping the gate position through a single 100
kHz cycle (10
µ
s = 50 steps) should result in the integrator outputs
going through a complete cycle of output voltage (full scale = ±2 to ±4 V
or ADC values of ±50 to ±100). By stepping the gate, one can verify
that the integrator can swing both positive and negative, can be reset
(just before the gates), and can change time constants. Measure the
integrator outputs at the input to the analog multiplexer U602.
Peak Detector Test
To test the signal peak detector (used for AGC purposes), apply a 100
kHz signal to the antenna input through the ANTENNA TERMINATOR.
In CAL MENU 1 set the attenuators for 64 dB and the gates for either
CAL 1 or CAL 2. As the input signal level is varied the peak detector
output (U116 pin 2) should be a DC voltage whose magnitude is about
the peak positive signal level of the LORAN OUTPUT.
