58
attenuation in 4 dB steps, and the last stage provides up to 3 dB of
attenuation in 1 dB steps.
The LORAN signal present after the filter stages is provided directly to
integrator stages to be discussed later, and is also demodulated for
AGC use. The AGC peak detector consists of D101, R146, C125, and
switch U409C, which is processor controlled to reset the peak detector
output. Op-amp U116A buffers the output of the detector. The amp is
configured to have unity gain. R147 and R148 form a divider which
limits the maximum signal excursion to the 5 V range which is tolerated
by the analog to digital converter used for gain control.
Transistor Q102 provides an indication of receiver lock to rear-panel
BNC connector J103. This output is pulled to +5 V through 10 k ohms,
and is normally high when the receiver is locked.
Microprocessor System (p. 3/14)
The FS700 is controlled by a 5 MHz CMOS version of the Z80. The 5
MHz clock is derived from the 10 MHz system reference. The unit's
firmware resides in a 27256 UVEPROM (U207). The processor also
uses 32 kilobytes of RAM. The RAM is also battery backed-up so that
instrument settings may be recalled after the unit is turned off. When the
+5 V supply is lost, power for the RAM is provided by a lithium battery
through blocking diode D202 and R201. Also, the chip select line for the
RAM is disabled on power down by the RESET line through Q201.
This prevents corruption of the RAM contents when power is lost.
U204 and U212 are demultiplexers which provide the 16 port strobes
used by the system. The buffered data bus is provided by U205, an 8-
bit bus transceiver that enables the bus only during I/O requests by the
Z80.
GPIB interfacing is provided by U209, a TMS9914A controller IC, and
by U210 and U211, which buffer data and control lines to the GPIB
connector. The controller IC generates the required control signals for
GPIB communication, as well as providing an interrupt to the processor
when data is received over the GPIB interface.
The front panel LCD interfaces through J201 to the buffered data bus,
along with two address lines, a chip select line, +5 V power and ground,
and a display contrast line. For high contrast and good readability, a
supertwist LCD design is used.
An 8254 triple programmable counter is used to generate a GRI interval
as well as two frequency sources. The two frequency sources are
cascaded so that the 5 MHz clocking frequency can be divided to lower
frequencies. Clocking for the GRI interval timer is provided by a 100
kHz clock source derived from the master 10 MHz source.
I/O Ports and Interrupt Drivers (p. 4/14)