PulseBlasterESR-PRO-200-cPCI
Summary
Output Signals
4 bracket-mounted BNC connectors, impedance matched to 50 Ω. 3.3 V LVTTL.
21 individually controlled digital output signals on IDC headers. 3.3 V LVTTL.
25 mA output current per output line.
4 status outputs on IDC header.
Timing Characteristics
Shortest pulse/delay: 1 clock cycle (5.0 ns).
Longest pulse/delay: 2
52
clock cycles (260 days).
Pulse resolution: 1 clock cycle (5.0 ns), regardless of pulse length.
Instruction Set (Program Flow)
User-programmable instruction execution time.
Subroutines can be nested up to 8 levels deep.
Loops can be nested up to 8 levels deep.
20-bit loop counters (maximum of 1,048,576 repetitions).
Branch range includes the entire memory.
Latency after trigger (WAIT state) – 8 clock cycle latency (40 ns at 200 MHz), adjustable to 20
seconds in duration.
External trigger and reset provide external control of the PulseBlaster device.
On-Board Clock
50 MHz on-board oscillator.
200 MHz internal clock frequency by use of a Phase-locked Loop.
External clock source may be used (contact SpinCore Technologies, Inc. for information on using an
external clock source).
Device Memory
Up to 4096 instructions.
External Input Specifications
External triggering and reset. Tolerance: 0.0 V minimum, 3.3 V maximum.
9
2017/01/24
